All instructionsArm64 · AArch64Address

ADRP

Form a PC-relative page address

Add a signed offset to the current instruction’s 4 KiB page base.

Armv8-A

Instruction forms

1 in this sample
FormBitsRequiresEncoding
ADRP Xd, label64Armv8-A1xx10000xxxxxxxxxxxxxxxxxxxxxxxx
64 bits

Operation

Pseudo-C · selected form
Xd = ((PC AND NOT(4095)) + page_displacement) mod 2^64

Simplified pseudocode for the selected form.

What to watch for

  • The offset is relative to this instruction, not the next instruction. No memory is accessed.
  • The low 12 result bits are zero; an ADD or load/store offset normally supplies the address within the page. The 4 KiB page unit is independent of the configured translation granule.

Architectural details

Flags
NZCV unchanged.
Destination
Writes the full 64-bit destination. Writes to ZR are discarded; SP is not accepted.
Encoding
1xx10000xxxxxxxxxxxxxxxxxxxxxxxx
Operands
  • Xdwrite · 64 bits
  • labeladdress expression · 64 bits
Coverage
Selected baseline A64 scalar register forms.
label
-4294967296 to 4294963200, in steps of 4096.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    MRS supplies encoding and availability conditions, not an exhaustive exception model.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Architectural references for this form

    These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.