A small reference, with depth.
Instruction Atlas connects exact instruction forms, C/C++ intrinsics, and editable explanations. This selected reference covers data movement, integer operations, control flow and SIMD floating point across x86-64 and AArch64.
What is covered
The sample includes 69 x86 families and68 AArch64 families. x86 vector forms cover selected register-only 128-bit legacy/VEX and 256-bit VEX encodings, including wider integer arithmetic, comparisons, multiplication, conversion and f32/f64 arithmetic. Scalar x86 coverage includes moves, logic, arithmetic, selected memory operands and conditional control flow. Arm coverage combines Neon references with scalar comparisons and aliases, branches, constant/address construction, shifts and selected memory widths/writeback.
162 selected forms have architectural fields still to import. 334 forms have no explorer. Reference coverage, intrinsic mappings, and explorer availability are tracked independently.
Unlisted addressing and encoding alternatives, atomic/exclusive accesses, APX, AVX-512, SVE, SME, floating-point simulation, full exception tables and performance measurements remain outside this release. CMP/CMN/TST pages link to their constrained base encodings. Alias spellings and width specializations can share source definitions; the counts above are not an ISA-completeness percentage. Every selected form identifies its scope.
Sources are versioned
| Source | Imported fields | Pinned revision |
|---|---|---|
| Intel SDM preview | Instruction forms, operand roles, encoding notation, feature flags; intrinsic signatures and mappings. | 4ebe7f0ac1bd |
| Arm architecture specification | 4349 A64 encoding definitions inventoried, with selected scalar, branch and memory forms published. Execution pseudocode is omitted from this open package; original explanations link to architectural references. | 2026-03_rel |
| Arm ACLE | Intrinsic signatures, AArch64 syntax, argument preparation and documented mappings. | 3a8fb2b1145b |
Normal builds read local snapshots and verify their SHA-256 checksums. Original explanatory prose and visualization functions are maintained separately from imported technical fields. The importer fails when a selected mapping disappears or a snapshot changes unexpectedly.
Intel labels its online SDM an architectural documentation preview. Its embedded Intrinsics Guide snapshot is version 3.6.9. Consult the published Intel manuals and Arm architecture documentation for authoritative architectural descriptions.
Reading the explorers
Element zero is always the least significant element, displayed on the left. These are register-element diagrams, not memory layouts. Each explorer evaluates the selected form and derives highlighted input dependencies from the same result. Values are shown as unsigned bit patterns.
The evaluator models the documented data transformation. It does not execute machine code or emulate privilege levels, faults, OS feature enablement, or complete processor state. FPSR.QC notes report whether the operation sets the bit, not its prior value.
Intrinsic mappings describe documented operations. A compiler may eliminate, combine, or select equivalent encodings. Cross-architecture links identify related operations and do not promise interchangeable behavior.
Attribution & terms
Intel source snapshots are preserved unmodified with their copyright and notices. The application imports technical identifiers, signatures, encoding facts, and the operation blocks shown under “Exact upstream semantics”; simplified explanations are independently written. Intel notices and terms.
Arm mappings are adapted from the Arm Neon Intrinsics Reference, © 2014–2026 Arm Limited and/or its affiliates and © 2021 Matt P. Dziubinski. Arm-derived data and accompanying explanations are distributed under CC BY-SA 4.0 with the ACLE additional patent license. Changes include selecting forms, normalizing fields, and adding explanatory material. Upstream terms are retained with each snapshot.
Arm architecture inventory: © 2010–2026 Arm Limited and/or its affiliates. Distributed under the BSD 3-Clause license and original notices. This data is separate from the ACLE adaptations above and supplies encodings for the selected scalar, branch and memory references.
Browse the sample
x86-64
PSHUFBShuffle bytesPUNPCKLBWInterleave low bytesPUNPCKHBWInterleave high bytesPSHUFDShuffle 32-bit elementsPADDBAdd bytesPADDUSBAdd unsigned bytes with saturationPSUBBSubtract bytesPXORBitwise exclusive ORPANDBitwise ANDPORBitwise ORPSLLWShift 16-bit elements leftPSRLWShift 16-bit elements rightPCMPEQBCompare bytes for equalityPACKUSWBPack signed words into unsigned bytesADDInteger additionSUBInteger subtractionCMPCompare integersLEACompute an effective addressMOVCopy dataMOVZXMove with zero extensionMOVSXMove with sign extensionMOVSXDMove with sign extensionANDBitwise ANDORBitwise ORXORBitwise exclusive ORTESTTest bitsJMPJump to a targetCALLCall a near targetRETReturn to the callerJZBranch if equal / zeroSETZSet byte if equal / zeroCMOVZMove if equal / zeroJNZBranch if not equal / nonzeroSETNZSet byte if not equal / nonzeroCMOVNZMove if not equal / nonzeroJLBranch if signed lessSETLSet byte if signed lessCMOVLMove if signed lessJNLBranch if signed greater or equalSETNLSet byte if signed greater or equalCMOVNLMove if signed greater or equalJBBranch if unsigned belowSETBSet byte if unsigned belowCMOVBMove if unsigned belowJNBBranch if unsigned above or equalSETNBSet byte if unsigned above or equalCMOVNBMove if unsigned above or equalPADDWAdd 16-bit elementsPSUBWSubtract 16-bit elementsPCMPEQWCompare equal 16-bit elementsPCMPGTWCompare signed greater 16-bit elementsPMULLWMultiply low 16-bit elementsPADDDAdd 32-bit elementsPSUBDSubtract 32-bit elementsPCMPEQDCompare equal 32-bit elementsPCMPGTDCompare signed greater 32-bit elementsPMULLDMultiply low 32-bit elementsPMOVSXBWWiden bytes to words with sign extensionPMOVZXBWWiden bytes to words with zero extensionPACKSSWBPack to signed 8-bit elements with saturationPACKSSDWPack to signed 16-bit elements with saturationADDPSAdd packed 32-bit floating-point valuesADDPDAdd packed 64-bit floating-point valuesSUBPSSubtract packed 32-bit floating-point valuesSUBPDSubtract packed 64-bit floating-point valuesMULPSMultiply packed 32-bit floating-point valuesMULPDMultiply packed 64-bit floating-point valuesDIVPSDivide packed 32-bit floating-point valuesDIVPDDivide packed 64-bit floating-point valuesAArch64 · scalar & AdvSIMD
TBLLook up bytes in a tableZIP1Interleave the lower halfZIP2Interleave the upper halfUZP1Collect even elementsUZP2Collect odd elementsTRN1Transpose even elementsTRN2Transpose odd elementsEXTExtract a byte windowREV64Reverse within 64-bit blocksUQADDAdd unsigned elements with saturationADDInteger additionSUBInteger subtractionANDBitwise ANDEORBitwise exclusive ORORRBitwise ORBSLSelect bits using a maskSHLShift 16-bit elements leftUSHRShift 16-bit elements rightADDSAdd and set flagsSUBSSubtract and set flagsBBranch to a labelBLCall a PC-relative targetBRBranch to a registerRETReturn through a registerCBZBranch if zeroCBNZBranch if nonzeroLDRLoad a register from memorySTRStore a register to memoryANDSBitwise AND and set flagsCMPCompare by subtractionCMNCompare by additionTSTCompare by bitwise ANDCSELSelect on conditionBLRCall through a registerTBZBranch on a clear bitTBNZBranch on a set bitMOVZConstruct a constant with zerosMOVNConstruct an inverted constantMOVKReplace one halfwordADRForm a PC-relative addressADRPForm a PC-relative page addressLSLVVariable left shiftLSRVVariable logical right shiftASRVVariable arithmetic right shiftRORVVariable right rotationLDRBLoad 8 bitsSTRBStore 8 bitsLDRHLoad 16 bitsSTRHStore 16 bitsLDRSBLoad with sign extensionLDRSHLoad with sign extensionLDRSWLoad with sign extensionLDURLoad with unscaled offsetSTURStore with unscaled offsetLDPLoad register pairSTPStore register pairMULMultiply integer elementsCMEQCompare elements for equalityCMGTCompare signed elements for greater thanSQADDAdd signed elements with saturationUSHLLWiden unsigned elementsSSHLLWiden signed elementsXTNNarrow by truncationSQXTNNarrow with signed saturationFADDAdd floating-point elementsFSUBSubtract floating-point elementsFMULMultiply floating-point elementsFDIVDivide floating-point elements