All instructionsx86-64Compare

CMOVNZ

/ CMOVNE

Move if not equal / nonzero

Test ZF = 0; select the source when true; otherwise retain the old value within the operand width.

CMOV

Instruction forms

2 in this sample
FormBitsRequiresEncoding
CMOVNZ r32_dst, r32_src32CMOV0F 45 /r
CMOVNZ r64_dst, r64_src64CMOVREX.W + 0F 45 /r
32 bits

Operation

Pseudo-C · selected form
dst = (ZF = 0) ? src : old_dst
R64[63:32] = 0

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

Source: intel/CMOVcc-Conditional-Move.xml/0

let result := if Condition_Holds(cond) then src2 else src1;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

  • Both data operands are registers in this selection. No memory access occurs.

Architectural details

Flags
Reads ZF = 0; leaves RFLAGS unchanged.
Destination
Writes the low 32 bits and clears the corresponding 64-bit register’s upper half. The 32-bit form clears the upper half even when the condition is false.
Encoding
0F 45 /r
Operands
  • r32_dstread / write · 32 bits
  • r32_srcread · 32 bits
Coverage
Selected register destinations only; memory and 16-bit conditional-move forms are outside this selection.
Conditions
  • not equal / nonzero: ZF = 0
Exception information & execution requirements
  • #UD

Imported exceptions are checks exposed by this XML form; memory, stack, instruction-fetch and called architectural helpers can introduce additional faults.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · CMOVcc-Conditional-Move.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
86f9029859c9dd03c872d527ca1c152a1acf3c497e41e9e7c27168981b103802
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.