All instructionsx86-64Compare

TEST

Test bits

Update flags from a bitwise AND without changing either input.

x86-64

Instruction forms

6 in this sample
FormBitsRequiresEncoding
TEST r32_dst, r32_src32x86-6485 /r
TEST r32_dst, imm3232x86-64F7 /0 iz
TEST m32_dst, r32_src32x86-6485 /r
TEST r64_dst, r64_src64x86-64REX.W + 85 /r
TEST r64_dst, imm3264x86-64REX.W + F7 /0 iz
TEST m64_dst, r64_src64x86-64REX.W + 85 /r
32 bits

Operation

Pseudo-C · selected form
b = src
result = dst AND b
// discard data result
update flags as described

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

Source: intel/TEST-Logical-Compare.xml/0

let result := src1 and src2;

RFLAGS.OF := 0b0;
RFLAGS.SF := result[operand_size-1];
RFLAGS.ZF := Bit(Is_Zero(result));
RFLAGS.AF := UNSPECIFIED : Bit;
RFLAGS.PF := Bit(Is_Parity_Even(result[0 +: 8]));
RFLAGS.CF := 0b0;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

  • No data destination is written; a 32-bit comparison does not clear any register’s upper half.

Architectural details

Flags
CF and OF are cleared. SF, ZF and PF reflect the result; AF is undefined.
Destination
Writes arithmetic flags only; data registers and memory are unchanged.
Encoding
85 /r
Operands
  • r32_dstread · 32 bits
  • r32_srcread · 32 bits
Coverage
Selected 32/64-bit register, immediate and ordinary memory forms in 64-bit execution mode; LOCK and APX forms are outside this selection.
Exception information & execution requirements
  • #UD

Imported exceptions are checks exposed by this XML form; memory, stack, instruction-fetch and called architectural helpers can introduce additional faults.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · TEST-Logical-Compare.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
b8b3e853c8a016d97a68d90b0469924c6a04dcc00b1ee3d88bf82dbd0d5daf9d
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.