A small reference, with depth.

What is covered

The sample includes 18 x86 families and28 AArch64 families. x86 vector forms cover selected register-only 128-bit legacy/VEX and 256-bit VEX encodings. ADD, SUB, CMP, and LEA include selected 32/64-bit forms in 64-bit mode. Arm coverage combines selected 128-bit Neon forms (including one- and two-register TBL tables) with 32/64-bit scalar arithmetic and logic, flag-setting comparisons, common branches and unsigned-offset LDR/STR.

53 selected forms have architectural fields still to import. 45 forms have no explorer. Reference coverage, intrinsic mappings, and explorer availability are tracked independently.

x86 memory operands, other Arm addressing modes, AVX-512, SVE, SME, floating-point simulation, full exception tables and performance measurements are outside this release. CMP/CMN aliases are explained on SUBS/ADDS pages without separate selected forms. Every page identifies its scope.

Sources are versioned

Normal builds read local snapshots and verify their SHA-256 checksums. Original explanatory prose and visualization functions are maintained separately from imported technical fields. The importer fails when a selected mapping disappears or a snapshot changes unexpectedly.

Intel labels its online SDM an architectural documentation preview. Its embedded Intrinsics Guide snapshot is version 3.6.9. Consult the published Intel manuals and Arm architecture documentation for authoritative architectural descriptions.

Reading the explorers

Element zero is always the least significant element, displayed on the left. These are register-element diagrams, not memory layouts. Each explorer evaluates the selected form and derives highlighted input dependencies from the same result. Values are shown as unsigned bit patterns.

The evaluator models the documented data transformation. It does not execute machine code or emulate privilege levels, faults, OS feature enablement, or complete processor state. FPSR.QC notes report whether the operation sets the bit, not its prior value.

Intrinsic mappings describe documented operations. A compiler may eliminate, combine, or select equivalent encodings. Cross-architecture links identify related operations and do not promise interchangeable behavior.

Attribution & terms

Intel source snapshots are preserved unmodified with their copyright and notices. The application imports technical identifiers, signatures, encoding facts, and the operation blocks shown under “Exact upstream semantics”; simplified explanations are independently written. Intel notices and terms.

Arm mappings are adapted from the Arm Neon Intrinsics Reference, © 2014–2026 Arm Limited and/or its affiliates and © 2021 Matt P. Dziubinski. Arm-derived data and accompanying explanations are distributed under CC BY-SA 4.0 with the ACLE additional patent license. Changes include selecting forms, normalizing fields, and adding explanatory material. Upstream terms are retained with each snapshot.

Browse the sample