All instructionsArm64 · AArch64Memory

LDR

Load a register from memory

Transfer a 32- or 64-bit value using a base and offset, optionally updating the base.

Armv8-A

Instruction forms

6 in this sample
FormBitsRequiresEncoding
LDR Wt, [Xn|SP{, #offset}]32Armv8-A1011100101xxxxxxxxxxxxxxxxxxxxxx
LDR Xt, [Xn|SP{, #offset}]64Armv8-A1111100101xxxxxxxxxxxxxxxxxxxxxx
LDR Wt, [Xn|SP, #offset]!32Armv8-A10111000010xxxxxxxxx11xxxxxxxxxx
LDR Wt, [Xn|SP], #offset32Armv8-A10111000010xxxxxxxxx01xxxxxxxxxx
LDR Xt, [Xn|SP, #offset]!64Armv8-A11111000010xxxxxxxxx11xxxxxxxxxx
LDR Xt, [Xn|SP], #offset64Armv8-A11111000010xxxxxxxxx01xxxxxxxxxx
64 bits

Operation

Pseudo-C · selected form
address = (base + offset) mod 2^64
Xt = Load64(address)

Simplified pseudocode for the selected form.

What to watch for

  • The assembly offset is in bytes: 0–32760, in multiples of 8; omission means zero. The encoding stores offset/8 in a 12-bit field.
  • The base is X0–X30 or SP, never a W register or XZR. The data register may be WZR/XZR; a load to ZR still performs the memory access, while a store from ZR writes zeros.
  • Memory byte order follows the current data endianness. This is an ordinary load/store, without acquire/release ordering.
  • SP use is subject to stack-alignment checks. Translation, access permissions, alignment controls and applicable memory-tag checks can cause faults; the pseudocode describes a successful access only.

Architectural details

Flags
NZCV unchanged.
Destination
Writes all 64 bits of the destination register. Writes to the zero register are discarded. The address base is not updated by writeback; if it names the destination register, the load result replaces it.
Encoding
1111100101xxxxxxxxxxxxxxxxxxxxxx
Operands
  • Xtwrite · 64 bits
  • Xn|SPread · 64 bits
  • offsetread · unsigned
  • [Xn|SP + offset]read · 64 bits
Coverage
64-bit general-register unsigned-offset addressing; the address base is always 64 bits. No base-register writeback.
Byte offset
0 to 32760, in steps of 8.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    The MRS snapshot supplies encoding and availability conditions, not a complete exception model.

    Data abort, alignment and applicable tag-check behavior depend on architectural configuration. The selected form has no base writeback.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Architectural references for this form

    These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.