STR
Store a register to memory
Transfer a 32- or 64-bit value using a base and offset, optionally updating the base.
| Form | Bits | Requires | Encoding |
|---|---|---|---|
STR Wt, [Xn|SP{, #offset}] | 32 | Armv8-A | 1011100100xxxxxxxxxxxxxxxxxxxxxx |
STR Xt, [Xn|SP{, #offset}] | 64 | Armv8-A | 1111100100xxxxxxxxxxxxxxxxxxxxxx |
STR Wt, [Xn|SP, #offset]! | 32 | Armv8-A | 10111000000xxxxxxxxx11xxxxxxxxxx |
STR Wt, [Xn|SP], #offset | 32 | Armv8-A | 10111000000xxxxxxxxx01xxxxxxxxxx |
STR Xt, [Xn|SP, #offset]! | 64 | Armv8-A | 11111000000xxxxxxxxx11xxxxxxxxxx |
STR Xt, [Xn|SP], #offset | 64 | Armv8-A | 11111000000xxxxxxxxx01xxxxxxxxxx |
Operation#
Pseudo-C · selected form
address = (base + offset) mod 2^64
Store64(address, Xt)What to watch for
- The assembly offset is in bytes: 0–32760, in multiples of 8; omission means zero. The encoding stores offset/8 in a 12-bit field.
- The base is X0–X30 or SP, never a W register or XZR. The data register may be WZR/XZR; a load to ZR still performs the memory access, while a store from ZR writes zeros.
- Memory byte order follows the current data endianness. This is an ordinary load/store, without acquire/release ordering.
- SP use is subject to stack-alignment checks. Translation, access permissions, alignment controls and applicable memory-tag checks can cause faults; the pseudocode describes a successful access only.
Architectural details#
- Flags
- NZCV unchanged.
- Destination
- Writes 8 bytes of memory. Source and base registers are unchanged.
- Encoding
1111100100xxxxxxxxxxxxxxxxxxxxxx- Operands
Xtread · 64 bitsXn|SPread · 64 bitsoffsetread · unsigned[Xn|SP + offset]write · 64 bits
- Coverage
- 64-bit general-register unsigned-offset addressing; the address base is always 64 bits. No base-register writeback.
- Byte offset
- 0 to 32760, in steps of 8.
Exception information & execution requirements
Complete exception conditions have not been imported.
The MRS snapshot supplies encoding and availability conditions, not a complete exception model.
Data abort, alignment and applicable tag-check behavior depend on architectural configuration. The selected form has no base writeback.
Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.
Sources & provenance#
Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.
Architectural references for this form
Arm · aarchmrs
- Revision
2026-03_rel- SHA-256
bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860- Terms
- BSD-3-Clause