All instructionsx86-64Arithmetic

PADDB

/ VPADDB

Add bytes

Add corresponding bytes, keeping the low eight bits of each sum.

SSE28-bit unsigned elements

Similar operations on Arm64:ADDvaddq_u8

Instruction forms

3 in this sample
FormBitsRequiresEncoding
PADDB xmm1, xmm2128SSE266 0F FC /r
VPADDB xmm1, xmm2, xmm3128AVXVEX.L0.66.0F.WIG FC /r
VPADDB ymm1, ymm2, ymm3256AVX2VEX.L1.66.0F.WIG FC /r
128 bits · 16 × 8-bit elements

Explore the operation

The interactive explorer is loading. The operation and reference details are available below.

Operation

Pseudo-C · selected form
dst[i] = (a[i] + b[i]) mod 256

Simplified pseudocode for the selected form.

What to watch for

  • Overflow wraps; no saturation or carry propagation between elements.

Corresponding intrinsics

C / C++ · selected form
_mm_add_epi8
__m128i _mm_add_epi8(__m128i a, __m128i b)
#include <emmintrin.h>SSE2

Documented instruction mapping; a compiler may use an equivalent encoding or optimize the operation away.

Documented mapping

PADDB xmm, xmm

Architectural details

Flags
Arithmetic flags unchanged.
Destination
Writes the low 128 bits; upper vector-register bits are preserved.
Encoding
66 0F FC /r
Operands
  • xmm1read / write · 128 bits (16 × 8) · unsigned
  • xmm2read · 128 bits (16 × 8) · unsigned
Coverage
Selected register-only 128/256-bit forms. Memory operands, MMX, and EVEX/AVX-512 forms are outside this sample.
Exception information & execution requirements
  • #NM
  • #UD

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · PADDB-PADDW-PADDD-PADDQ-Add-Packed-Integers.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
fb59f15d568d52ab683649e05b1095e9f44854a24170853a0c5e38ebb59ff851
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗
Intel · intrinsics.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
6762a50652a35ef663fd532ed83b789d19bbc2ac7e94b1771f19d666d96c2c30
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.