All instructionsArm64 · AArch64Arithmetic

ADD

Integer addition

Add scalar integers or corresponding vector elements, keeping the result within the selected width.

AdvSIMD8-bit unsigned elements

Similar operations on other architectures:PADDB_mm_add_epi8ADD

Instruction forms

7 in this sample
FormBitsRequiresEncoding
Vector integer
ADD Vd.16B,Vn.16B,Vm.16B128AdvSIMD—
ADD Vd.8H,Vn.8H,Vm.8H128AdvSIMD—
ADD Vd.4S,Vn.4S,Vm.4S128AdvSIMD—
Scalar integer
ADD Wd, Wn, Wm{, shift #amount}32Armv8-A00001011xx0xxxxxxxxxxxxxxxxxxxxx
ADD Wd|WSP, Wn|WSP, #imm{, LSL #12}32Armv8-A000100010xxxxxxxxxxxxxxxxxxxxxxx
ADD Xd, Xn, Xm{, shift #amount}64Armv8-A10001011xx0xxxxxxxxxxxxxxxxxxxxx
ADD Xd|SP, Xn|SP, #imm{, LSL #12}64Armv8-A100100010xxxxxxxxxxxxxxxxxxxxxxx
128 bits · 16 × 8-bit elements

Add corresponding bytes, keeping the low eight bits of each sum.

Explore the operation

The interactive explorer is loading. The operation and reference details are available below.

Operation

Pseudo-C · selected form
dst[i] = (a[i] + b[i]) mod 256

Simplified pseudocode for the selected form.

What to watch for

  • This selected form performs independent byte additions.
  • Vector ADD does not update NZCV.

Corresponding intrinsics

C / C++ · selected form
vaddq_u8
uint8x16_t vaddq_u8( uint8x16_t a, uint8x16_t b)
#include <arm_neon.h>AdvSIMD

AArch64 mapping documented by ACLE; compiler output depends on optimization and context.

Documented mapping

ADD Vd.16B,Vn.16B,Vm.16B

Architectural details

Flags
NZCV unchanged.
Destination
Writes all 128 bits of the selected V destination register.
Encoding
Encoding details have not been imported for this form.
Operands
a -> Vn.16B b -> Vm.16B
  • Vdwrite · 128 bits (16 × 8) · unsigned
  • aread · 128 bits (16 × 8) · unsigned
  • bread · 128 bits (16 × 8) · unsigned
Coverage
Selected 128-bit AdvSIMD byte, halfword and word arrangements. Scalar forms, if present, have a separate variant. Other vector arrangements and SVE/SME are outside this variant.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    Availability depends on execution-level controls for AdvSIMD. This ACLE import does not contain an exhaustive architectural exception list.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Arm · advsimd.md
    Revision
    3a8fb2b1145b27ba0a9110ed32f3a6cfdad6c002
    SHA-256
    722dcf758d7a6dbbab54210d55bbce73a6db7691bb4092112375bf096563fd73
    Terms
    CC-BY-SA-4.0 AND Apache-Patent-License
    View pinned upstream file ↗
    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.