ADD

Integer addition

Add the source to the destination and update the arithmetic flags.

x86-64

Similar operations on Arm64:ADDvaddq_u8

Form	Bits	Requires	Encoding
`ADD r32_dst, r32_src`	32	x86-64	`01 /r`
`ADD r64_dst, r64_src`	64	x86-64	`REX.W + 01 /r`
`ADD r32_dst, imm8`	32	x86-64	`83 /0 ib`
`ADD r32_dst, imm32`	32	x86-64	`81 /0 iz`
`ADD r32_dst, m32_src`	32	x86-64	`03 /r`
`ADD m32_dst, r32_src`	32	x86-64	`01 /r`
`ADD r64_dst, imm8`	64	x86-64	`REX.W + 83 /0 ib`
`ADD r64_dst, imm32`	64	x86-64	`REX.W + 81 /0 iz`
`ADD r64_dst, m64_src`	64	x86-64	`REX.W + 03 /r`
`ADD m64_dst, r64_src`	64	x86-64	`REX.W + 01 /r`

64 bits

Operation#

Pseudo-C · selected form

dst = (dst + src) mod 2^width
update OF, SF, ZF, AF, CF, PF

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

Source: intel/ADD-Add.xml/0

let (result, carry_out, overflow, alternative_carry) := Add(src1, src2);

RFLAGS.OF := overflow;
RFLAGS.SF := result[operand_size-1];
RFLAGS.ZF := Bit(Is_Zero(result));
RFLAGS.AF := alternative_carry;
RFLAGS.PF := Bit(Is_Parity_Even(result[0 +: 8]));
RFLAGS.CF := carry_out;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

This sample covers 32-bit and 64-bit register operands.
A 32-bit destination write clears the upper 32 bits of its 64-bit register.

Architectural details#

Flags: Updates OF, SF, ZF, AF, CF, and PF.
Destination: Writes the destination register.
Encoding: REX.W + 01 /r
Operands: r64_dstread / write · 64 bits
r64_srcread · 64 bits
Coverage: Selected 32/64-bit register, immediate and ordinary memory forms in 64-bit execution mode; LOCK and APX forms are outside this selection.

Exception information & execution requirements

#UD

No memory is accessed by this selected form. Consult the source for execution-mode and prefix exceptions.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance#

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · ADD-Add.xml

Revision: 4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256: f0b2e471ddf005c71406c79482a3df91e1575fa49830b4fe7e07f3d77a734690
Terms: Intel SDM terms; see License.md

View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.

Instruction forms

Operation#

Standard variant

What to watch for

Architectural details#

Sources & provenance#