All instructionsArm64 · AArch64Arithmetic

UQADD

Add unsigned elements with saturation

Add corresponding unsigned elements and clamp at the selected element width.

AdvSIMD8-bit unsigned elements

Similar operations on x86-64:PADDUSB_mm_adds_epu8

Instruction forms

3 in this sample
FormBitsRequiresEncoding
UQADD Vd.16B,Vn.16B,Vm.16B128AdvSIMD—
UQADD Vd.8H,Vn.8H,Vm.8H128AdvSIMD—
UQADD Vd.4S,Vn.4S,Vm.4S128AdvSIMD—
128 bits · 16 × 8-bit elements

Explore the operation

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Operation

Pseudo-C · selected form
dst[i] = min(a[i] + b[i], 255)
if any sum > 255: FPSR.QC = 1

Simplified pseudocode for the selected form.

What to watch for

  • Saturation sets the cumulative FPSR.QC bit. It stays set until explicitly cleared.

Corresponding intrinsics

C / C++ · selected form
vqaddq_u8
uint8x16_t vqaddq_u8( uint8x16_t a, uint8x16_t b)
#include <arm_neon.h>AdvSIMD

AArch64 mapping documented by ACLE; compiler output depends on optimization and context.

Documented mapping

UQADD Vd.16B,Vn.16B,Vm.16B

Architectural details

Flags
NZCV unchanged. Saturation sets the sticky FPSR.QC bit.
Destination
Writes all 128 bits of the selected V destination register.
Encoding
Encoding details have not been imported for this form.
Operands
a -> Vn.16B b -> Vm.16B
  • Vdwrite · 128 bits (16 × 8) · unsigned
  • aread · 128 bits (16 × 8) · unsigned
  • bread · 128 bits (16 × 8) · unsigned
Coverage
Selected 128-bit AdvSIMD byte, halfword and word arrangements. Scalar forms, if present, have a separate variant. Other vector arrangements and SVE/SME are outside this variant.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    Availability depends on execution-level controls for AdvSIMD. This ACLE import does not contain an exhaustive architectural exception list.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Arm · advsimd.md
    Revision
    3a8fb2b1145b27ba0a9110ed32f3a6cfdad6c002
    SHA-256
    722dcf758d7a6dbbab54210d55bbce73a6db7691bb4092112375bf096563fd73
    Terms
    CC-BY-SA-4.0 AND Apache-Patent-License
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.