All instructionsArm64 · AArch64Control flow

CBNZ

Branch if nonzero

Test a register and branch to a PC-relative target when it is nonzero, leaving NZCV unchanged.

Armv8-A

Instruction forms

2 in this sample
FormBitsRequiresEncoding
CBNZ Wt, label32Armv8-A00110101xxxxxxxxxxxxxxxxxxxxxxxx
CBNZ Xt, label64Armv8-A10110101xxxxxxxxxxxxxxxxxxxxxxxx
64 bits

Operation

Pseudo-C · selected form
PC = (Rt != 0) ? PC + displacement : PC + 4

Simplified pseudocode for the selected form.

What to watch for

  • The displacement is measured in bytes from the address of this instruction and must be a multiple of 4. The signed encoded field is scaled by 4.
  • This tests the selected register width directly; it neither reads nor writes NZCV. WZR/XZR is accepted and always tests as zero.

Architectural details

Flags
NZCV unchanged.
Destination
Writes PC. General-purpose registers are unchanged.
Encoding
10110101xxxxxxxxxxxxxxxxxxxxxxxx
Operands
  • Xtread · 64 bits
  • labeladdress expression · 64 bits
  • PCread / write · 64 bits
Coverage
Selected baseline A64 control flow. Conditional flag-based branches, authenticated branches and architectural state beyond PC/link-register effects are outside this selection.
PC-relative byte displacement
-1048576 to 1048572, in steps of 4.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    The MRS snapshot supplies encoding and availability conditions, not a complete exception model.

    Target instruction fetches can fault. Control-flow hardening and later architectural extensions are not described by this simplified operation.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Architectural references for this form

    These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.