All instructionsArm64 · AArch64Logical

EOR

Bitwise exclusive OR

Set each bit where the scalar or vector inputs differ.

AdvSIMD8-bit bits elements

Similar operations on x86-64:PXOR_mm_xor_si128

Instruction forms

3 in this sample
FormBitsRequiresEncoding
Vector integer
EOR Vd.16B,Vn.16B,Vm.16B128AdvSIMD—
Scalar integer
EOR Wd, Wn, Wm{, shift #amount}32Armv8-A01001010xx0xxxxxxxxxxxxxxxxxxxxx
EOR Xd, Xn, Xm{, shift #amount}64Armv8-A11001010xx0xxxxxxxxxxxxxxxxxxxxx
128 bits · 16 × 8-bit elements

Set each result bit when the corresponding input bits differ.

Explore the operation

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Operation

Pseudo-C · selected form
dst = a XOR b

Simplified pseudocode for the selected form.

What to watch for

  • This selected form operates on the full vector register.

Corresponding intrinsics

C / C++ · selected form
veorq_u8
uint8x16_t veorq_u8( uint8x16_t a, uint8x16_t b)
#include <arm_neon.h>AdvSIMD

AArch64 mapping documented by ACLE; compiler output depends on optimization and context.

Documented mapping

EOR Vd.16B,Vn.16B,Vm.16B

Architectural details

Flags
NZCV unchanged.
Destination
Writes all 128 bits of the selected V destination register.
Encoding
Encoding details have not been imported for this form.
Operands
a -> Vn.16B b -> Vm.16B
  • Vdwrite · 128 bits (16 × 8)
  • aread · 128 bits (16 × 8) · unsigned
  • bread · 128 bits (16 × 8) · unsigned
Coverage
Selected 128-bit AArch64 AdvSIMD (Neon) forms from ACLE. Other vector arrangements, SVE and SME forms are outside this variant.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    Availability depends on execution-level controls for AdvSIMD. This ACLE import does not contain an exhaustive architectural exception list.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Arm · advsimd.md
    Revision
    3a8fb2b1145b27ba0a9110ed32f3a6cfdad6c002
    SHA-256
    722dcf758d7a6dbbab54210d55bbce73a6db7691bb4092112375bf096563fd73
    Terms
    CC-BY-SA-4.0 AND Apache-Patent-License
    View pinned upstream file ↗
    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.