All instructionsArm64 · AArch64Control flow

RET

Return through a register

Branch to a register address with a subroutine-return hint; the default register is X30.

Armv8-A

Instruction forms

1 in this sample
FormBitsRequiresEncoding
RET {Xn}64Armv8-A1101011001011111000000xxxxx00000
64 bits

Operation

Pseudo-C · selected form
PC = Xn  // Xn defaults to X30; return hint

Simplified pseudocode for the selected form.

What to watch for

  • The target is a 64-bit address; instruction alignment and fetch permissions still apply. SP is not accepted.
  • Omitting Xn selects X30. RET does not restore registers, adjust SP or authenticate a pointer. The return hint distinguishes it from BR.

Architectural details

Flags
NZCV unchanged.
Destination
Writes PC. General-purpose registers are unchanged.
Encoding
1101011001011111000000xxxxx00000
Operands
  • Xn (X30 if omitted)read · 64 bits
  • PCwrite · 64 bits
Coverage
Selected baseline A64 control flow. Conditional flag-based branches, authenticated branches and architectural state beyond PC/link-register effects are outside this selection.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    The MRS snapshot supplies encoding and availability conditions, not a complete exception model.

    Target instruction fetches can fault. Control-flow hardening and later architectural extensions are not described by this simplified operation.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Architectural references for this form

    These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.