All instructionsArm64 · AArch64Rearrange

TBL

Look up bytes in a table

Use each index byte to select a byte from one or two table registers. Indices outside the table produce zero.

AdvSIMD8-bit bits elements

Similar operations on x86-64:PSHUFB_mm_shuffle_epi8

Instruction forms

2 in this sample
FormBitsRequiresEncoding
TBL Vd.16B,{Vn.16B},Vm.16B128AdvSIMD—
TBL Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B128AdvSIMD—
128 bits · 16 × 8-bit elements

Explore the operation

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Operation

Pseudo-C · selected form
dst[i] = index[i] < table.length ? table[index[i]] : 0

Simplified pseudocode for the selected form.

What to watch for

  • All eight index bits are used. With one table register, an index of 16 produces zero.
  • The two-register form treats the table as 32 consecutive bytes.

Corresponding intrinsics

C / C++ · selected form
vqtbl1q_u8
uint8x16_t vqtbl1q_u8( uint8x16_t t, uint8x16_t idx)
#include <arm_neon.h>AdvSIMD

AArch64 mapping documented by ACLE; compiler output depends on optimization and context.

Documented mapping

TBL Vd.16B,{Vn.16B},Vm.16B

Architectural details

Flags
NZCV unchanged.
Destination
Writes all 128 bits of the selected V destination register.
Encoding
Encoding details have not been imported for this form.
Operands
t -> Vn.16B idx -> Vm.16B
  • Vdwrite · 128 bits (16 × 8)
  • tread · 128 bits (16 × 8) · unsigned
  • idxread · 128 bits (16 × 8) · unsigned
Coverage
Selected 128-bit AArch64 AdvSIMD (Neon) forms from ACLE. Scalar, other element arrangements, SVE, and SME forms are outside this sample.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    Availability depends on execution-level controls for AdvSIMD. This ACLE import does not contain an exhaustive architectural exception list.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Arm · advsimd.md
    Revision
    3a8fb2b1145b27ba0a9110ed32f3a6cfdad6c002
    SHA-256
    722dcf758d7a6dbbab54210d55bbce73a6db7691bb4092112375bf096563fd73
    Terms
    CC-BY-SA-4.0 AND Apache-Patent-License
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.