PMOVZXBW

/ VPMOVZXBW

Widen bytes to words with zero extension

Extend selected low bytes to 16-bit elements.

SSE4.116-bit unsigned elements

Similar operations on Arm64:USHLLvmovl_u8

Form	Bits	Requires	Encoding
`PMOVZXBW xmm1, xmm2`	128	SSE4.1	`66 0F 38 30 /r`
`VPMOVZXBW xmm1, xmm2`	128	AVX	`VEX.L0.66.0F38.WIG 30 /r`
`VPMOVZXBW ymm, xmm`	256	AVX2	`VEX.L1.66.0F38.WIG 30 /r`

128 bits · 8 × 16-bit elements

Operation#

Pseudo-C · selected form

dst[i] = zero_extend(low_source_bytes[i], 16)

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

Source: intel/PMOVZX-Packed-Move-With-Zero-Extend.xml/0

let elements := result_size / result_element_size;
var result := Zero(result_size);
for i := 0 to elements-1 do
let op := src[i *: element_size];
let r := Zero_Extend(op, result_element_size);
result[i *: result_element_size] := r;
endfor;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

Only the low 64 source bits are read; the destination is 128 bits wide. The source is an XMM register in both vector widths.

Corresponding intrinsics#

C / C++ · selected form

_mm_cvtepu8_epi16

Open example

__m128i _mm_cvtepu8_epi16(__m128i a)

#include <smmintrin.h>SSE4.1

Documented instruction mapping; a compiler may use an equivalent encoding or optimize the operation away.

Documented mapping

PMOVZXBW xmm, xmm

Architectural details#

Flags: RFLAGS unchanged.
Destination: Writes the low 128 bits; upper vector-register bits are preserved.
Encoding: 66 0F 38 30 /r
Operands: xmm1write · 128 bits (8 × 16) · unsigned
xmm2read · 64 bits (8 × 8) · unsigned
Coverage: Selected register-only 128/256-bit legacy and VEX forms. Memory, MMX, EVEX/AVX-512 and scalar floating-point forms are outside this selection.

Exception information & execution requirements

#NM
#UD

Feature availability, operating-system vector-state enablement and applicable floating-point exception controls still apply.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance#

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · PMOVZX-Packed-Move-With-Zero-Extend.xml

Revision: 4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256: 1df4548e9de7b42cdfb1fde0403c726fbf727f8e176a06095b972def1627b9c5
Terms: Intel SDM terms; see License.md

View pinned upstream file ↗

Intel · intrinsics.xml

Revision: 4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256: 6762a50652a35ef663fd532ed83b789d19bbc2ac7e94b1771f19d666d96c2c30
Terms: Intel SDM terms; see License.md