USHLL

Widen unsigned elements

Widen unsigned elements in the selected vector arrangement.

AdvSIMD16-bit unsigned elements

Similar operations on x86-64:PMOVZXBW_mm_cvtepu8_epi16

Form	Bits	Requires	Encoding
`USHLL Vd.8H,Vn.8B,#0`	128	AdvSIMD	—
`USHLL Vd.4S,Vn.4H,#0`	128	AdvSIMD	—

128 bits · 8 × 16-bit elements

Operation#

Pseudo-C · selected form

dst[i] = zero_extend(a[i], 16)

Simplified pseudocode for the selected form.

What to watch for

These selected ACLE mappings fix the shift at zero. Other SSHLL/USHLL shifts and the “2” high-half variants are outside this selection.

Corresponding intrinsics#

C / C++ · selected form

vmovl_u8

Open example

uint16x8_t vmovl_u8(uint8x8_t a)

#include <arm_neon.h>AdvSIMD

AArch64 mapping documented by ACLE; compiler output depends on optimization and context.

Documented mapping

USHLL Vd.8H,Vn.8B,#0

Architectural details#

Flags: NZCV unchanged.
Destination: Writes all 128 bits of Vd.
Encoding: Encoding details have not been imported for this form.
Operands: a -> Vn.8B
Vdwrite · 128 bits (8 × 16) · unsigned
Vnread · 64 bits (8 × 8) · unsigned
shift (fixed in this selection)read · unsigned
Coverage: Selected USHLL Vd.8H,Vn.8B,#0 arrangement. Shift is fixed at zero.
shift (fixed in this selection): 0.

Exception information & execution requirements

Complete exception conditions have not been imported.

AdvSIMD/FP access can be trapped by execution-level controls. The ACLE source does not provide an exhaustive exception model.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

Sources & provenance#

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Architectural references for this form

Arm Instruction Set Reference Guide 1.0, D6.272; Parts B1/B2 ↗

These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

Arm · advsimd.md

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View pinned upstream file ↗