JMP

Jump to a target

Continue execution at a relative or register target.

x86-64

Instruction forms

3 in this sample
FormBitsRequiresEncoding
JMP rel8—x86-64EB cb
JMP rel32—x86-64E9 cd
JMP r6464x86-64FF /4
No fixed data width

Operation

Pseudo-C · selected form
target = next_RIP + sign_extend(displacement, 64)
RIP = target

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

Source: intel/JMP-Jump.xml/1

let new_rip :=
if is_indirect then
Zero_Extend(src, 64)
else
Relative_Branch_Wrap(context.operand_size, Next_IP + Sign_Extend(src, 64));

Check_New_RIP?(CS, new_rip);
Branch_Near(new_rip);

if is_indirect and Is_End_Branch_Enabled_And_Not_Suppressed(CPL) then
if IA32_CET[CPL].NO_TRACK_EN == 0b0 or not is_no_track then
CET::Set_Tracker_Status(CPL);
endif;
endif;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

  • Only near control transfers in 64-bit mode are selected. Far transfers, compatibility mode and CET shadow-stack/indirect-branch state are outside the simplified operation.
  • Targets must meet architectural fetch and canonical-address requirements. Stack accesses can fault for CALL/RET.
  • The signed byte displacement is relative to the end of this instruction (next RIP).

Architectural details

Flags
RFLAGS unchanged.
Destination
Writes RIP; registers and the stack are otherwise unchanged.
Encoding
EB cb
Operands
  • rel8read · 8 bits
Coverage
Selected near control transfers in 64-bit execution mode, using a 64-bit stack address size.
rel8
-128 to 127.
Exception information & execution requirements
  • #UD

Imported exceptions are checks exposed by this XML form; memory, stack, instruction-fetch and called architectural helpers can introduce additional faults.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · JMP-Jump.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
7ba4012a13a4d1cc3a1870608a85aef446726e55530945517433c02790768180
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.