All instructionsArm64 · AArch64Control flow

TBNZ

Branch on a set bit

Test one register bit and branch without using NZCV.

Armv8-A

Instruction forms

2 in this sample
FormBitsRequiresEncoding
TBNZ Wt, #bit, label32Armv8-A00110111xxxxxxxxxxxxxxxxxxxxxxxx
TBNZ Xt, #bit, label64Armv8-Ax0110111xxxxxxxxxxxxxxxxxxxxxxxx
32 bits

Operation

Pseudo-C · selected form
PC = (Rt[bit] != 0) ? PC + displacement : PC + 4

Simplified pseudocode for the selected form.

What to watch for

  • X spelling permits bits 0–63; W spelling permits only bits 0–31. These spellings share an encoding for low bits.
  • The byte displacement is measured from this instruction, in multiples of four.

Architectural details

Flags
NZCV unchanged.
Destination
Writes PC; data registers are unchanged.
Encoding
00110111xxxxxxxxxxxxxxxxxxxxxxxx
Operands
  • Wtread · 32 bits
  • bitread
  • labeladdress expression · 64 bits
  • PCwrite · 64 bits
Coverage
W and X assembly spellings of the test-bit branch encoding; their low-bit cases overlap.
bit
0 to 31.
label
-32768 to 32764, in steps of 4.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    MRS supplies encoding and availability conditions, not an exhaustive exception model.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Architectural references for this form

    These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.