PADDW

/ VPADDW

Add 16-bit elements

Compute each 16-bit result independently, keeping the low 16 bits.

SSE216-bit unsigned elements

Form	Bits	Requires	Encoding
`PADDW xmm1, xmm2`	128	SSE2	`66 0F FD /r`
`VPADDW xmm1, xmm2, xmm3`	128	AVX	`VEX.L0.66.0F.WIG FD /r`
`VPADDW ymm1, ymm2, ymm3`	256	AVX2	`VEX.L1.66.0F.WIG FD /r`

128 bits · 8 × 16-bit elements

Operation#

Pseudo-C · selected form

dst[i] = (a[i] + b[i]) mod 2^16

Simplified pseudocode for the selected form.

What to watch for

Each element operates independently; arithmetic does not propagate carry between elements.

Corresponding intrinsics#

C / C++ · selected form

_mm_add_epi16

Open example

__m128i _mm_add_epi16(__m128i a, __m128i b)

#include <emmintrin.h>SSE2

Documented instruction mapping; a compiler may use an equivalent encoding or optimize the operation away.

Documented mapping

PADDW xmm, xmm

Architectural details#

Flags: RFLAGS unchanged.
Destination: Writes the low 128 bits; upper vector-register bits are preserved.
Encoding: 66 0F FD /r
Operands: xmm1read / write · 128 bits (8 × 16) · unsigned
xmm2read · 128 bits (8 × 16) · unsigned
Coverage: Selected register-only 128/256-bit legacy and VEX forms. Memory, MMX, EVEX/AVX-512 and scalar floating-point forms are outside this selection.

Exception information & execution requirements

#NM
#UD

Feature availability, operating-system vector-state enablement and applicable floating-point exception controls still apply.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance#

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · PADDB-PADDW-PADDD-PADDQ-Add-Packed-Integers.xml

Revision: 4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256: fb59f15d568d52ab683649e05b1095e9f44854a24170853a0c5e38ebb59ff851
Terms: Intel SDM terms; see License.md

View pinned upstream file ↗

Intel · intrinsics.xml

Revision: 4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256: 6762a50652a35ef663fd532ed83b789d19bbc2ac7e94b1771f19d666d96c2c30
Terms: Intel SDM terms; see License.md