MULPS

/ VMULPS

Multiply packed 32-bit floating-point values

Apply floating-point * independently to each pair of 32-bit elements, using MXCSR controls.

SSE32-bit float elements

Similar operations on Arm64:FMULvmulq_f32

Instruction forms

3 in this sample
FormBitsRequiresEncoding
MULPS xmm1, xmm2128SSENP 0F 59 /r
VMULPS xmm1, xmm2, xmm3128AVXVEX.L0.NP.0F.WIG 59 /r
VMULPS ymm1, ymm2, ymm3256AVXVEX.L1.NP.0F.WIG 59 /r
128 bits · 4 × 32-bit elements

Operation

Pseudo-C · selected form
dst[i] = fp32_operation(a[i] * b[i], MXCSR)
update floating-point status or raise an unmasked exception as required

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

Source: intel/MULPS-Multiply-Packed-Single-Precision-Floating-Point-Values.xml/0

let elements := register_size / element_size;
let denormals_are_zeros := FP::Get_DAZ(element_size);
let flush_subnormals := FP::Get_FTZ(element_size);
let mask_underflow := MXCSR.UM == 0b1;
let exception_masks := MXCSR.Exception_Masks;
let suppress_all_exceptions := (context.evex_b == 0b1) and (mod == 0b11);
let rc := if (context.evex_b == 0b1) and (mod == 0b11) then context.evex_LLRC else MXCSR.RC;
let rounding_mode := FP::Decode_Rounding_Mode(rc);
var all_exceptions := Zero(6);
var result := Zero(register_size);
for i := 0 to elements-1 do
let op1 := src1[i *: element_size];
let op2 := src2[i *: element_size];
let (r, exceptions) := FP::Arithmetic(FP_MUL, op1, op2, denormals_are_zeros, rounding_mode, flush_subnormals, mask_underflow);
all_exceptions := all_exceptions or exceptions;
result[i *: element_size] := r;
endfor;
let reported_exceptions := if suppress_all_exceptions then Zero(6) else all_exceptions;
FP::Check_Exceptions?(reported_exceptions, exception_masks);

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

  • MXCSR selects rounding, exception masks and supported denormal/flush-to-zero controls. Results for NaNs, infinities, signed zeros and subnormals follow those architectural rules.
  • Floating-point status can change even though RFLAGS does not. This reference does not emulate floating-point arithmetic.

Corresponding intrinsics

C / C++ · selected form
__m128 _mm_mul_ps(__m128 a, __m128 b)
#include <xmmintrin.h>SSE

Documented instruction mapping; a compiler may use an equivalent encoding or optimize the operation away.

Documented mapping

MULPS xmm, xmm

Architectural details

Flags
RFLAGS unchanged. MXCSR floating-point status may be updated.
Destination
Writes the low 128 bits; upper vector-register bits are preserved.
Encoding
NP 0F 59 /r
Operands
  • xmm1read / write · 128 bits (4 × 32) · float
  • xmm2read · 128 bits (4 × 32) · float
Coverage
Selected register-only 128/256-bit legacy and VEX forms. Memory, MMX, EVEX/AVX-512 and scalar floating-point forms are outside this selection.
Exception information & execution requirements
  • #NM
  • #UD

Feature availability, operating-system vector-state enablement and applicable floating-point exception controls still apply.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · MULPS-Multiply-Packed-Single-Precision-Floating-Point-Values.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
965aaafbd8ba3e97b3a95e5f5e9011ae5554f6903a39a380ac26e2b46a511ab6
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗
Intel · intrinsics.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
6762a50652a35ef663fd532ed83b789d19bbc2ac7e94b1771f19d666d96c2c30
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.