CMEQ

Compare elements for equality

Compare elements for equality in the selected vector arrangement.

AdvSIMD16-bit unsigned elements

Similar operations on other architectures:PCMPEQW_mm_cmpeq_epi16PCMPEQD_mm_cmpeq_epi32

Form	Bits	Requires	Encoding
`CMEQ Vd.8H,Vn.8H,Vm.8H`	128	AdvSIMD	—
`CMEQ Vd.4S,Vn.4S,Vm.4S`	128	AdvSIMD	—

128 bits · 8 × 16-bit elements

Operation#

Pseudo-C · selected form

dst[i] = (a[i] == b[i]) ? 65535 : 0

Simplified pseudocode for the selected form.

What to watch for

Integer element operations are independent; there is no carry propagation between lanes.
The result is a bit mask, not scalar 0/1. CMGT uses signed input comparisons; CMEQ compares equal bit patterns.

Corresponding intrinsics#

C / C++ · selected form

vceqq_u16

Open example

uint16x8_t vceqq_u16( uint16x8_t a, uint16x8_t b)

#include <arm_neon.h>AdvSIMD

AArch64 mapping documented by ACLE; compiler output depends on optimization and context.

Documented mapping

CMEQ Vd.8H,Vn.8H,Vm.8H

Architectural details#

Flags: NZCV unchanged.
Destination: Writes all 128 bits of Vd.
Encoding: Encoding details have not been imported for this form.
Operands: a -> Vn.8H b -> Vm.8H
Vdwrite · 128 bits (8 × 16) · unsigned
Vnread · 128 bits (8 × 16) · unsigned
Vmread · 128 bits (8 × 16) · unsigned
Coverage: Selected CMEQ Vd.8H,Vn.8H,Vm.8H arrangement.

Exception information & execution requirements

Complete exception conditions have not been imported.

AdvSIMD/FP access can be trapped by execution-level controls. The ACLE source does not provide an exhaustive exception model.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

Sources & provenance#

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Architectural references for this form

Arm Instruction Set Reference Guide 1.0, D6.15; Parts B1/B2 ↗

These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

Arm · advsimd.md

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Terms: CC-BY-SA-4.0 AND Apache-Patent-License

View pinned upstream file ↗