ADDPD
/ VADDPDAdd packed 64-bit floating-point values
Apply floating-point + independently to each pair of 64-bit elements, using MXCSR controls.
Similar operations on Arm64:FADDvaddq_f32
| Form | Bits | Requires | Encoding |
|---|---|---|---|
ADDPD xmm1, xmm2 | 128 | SSE2 | 66 0F 58 /r |
VADDPD xmm1, xmm2, xmm3 | 128 | AVX | VEX.L0.66.0F.WIG 58 /r |
VADDPD ymm1, ymm2, ymm3 | 256 | AVX | VEX.L1.66.0F.WIG 58 /r |
Operation#
Pseudo-C · selected form
dst[i] = fp64_operation(a[i] + b[i], MXCSR)
update floating-point status or raise an unmasked exception as requiredExact upstream semantics
Standard variant
let elements := register_size / element_size;
let denormals_are_zeros := FP::Get_DAZ(element_size);
let flush_subnormals := FP::Get_FTZ(element_size);
let mask_underflow := MXCSR.UM == 0b1;
let exception_masks := MXCSR.Exception_Masks;
let suppress_all_exceptions := (context.evex_b == 0b1) and (mod == 0b11);
let rc := if (context.evex_b == 0b1) and (mod == 0b11) then context.evex_LLRC else MXCSR.RC;
let rounding_mode := FP::Decode_Rounding_Mode(rc);
var all_exceptions := Zero(6);
var result := Zero(register_size);
for i := 0 to elements-1 do
let op1 := src1[i *: element_size];
let op2 := src2[i *: element_size];
let (r, exceptions) := FP::Arithmetic(FP_ADD, op1, op2, denormals_are_zeros, rounding_mode, flush_subnormals, mask_underflow);
all_exceptions := all_exceptions or exceptions;
result[i *: element_size] := r;
endfor;
let reported_exceptions := if suppress_all_exceptions then Zero(6) else all_exceptions;
FP::Check_Exceptions?(reported_exceptions, exception_masks);What to watch for
- MXCSR selects rounding, exception masks and supported denormal/flush-to-zero controls. Results for NaNs, infinities, signed zeros and subnormals follow those architectural rules.
- Floating-point status can change even though RFLAGS does not. This reference does not emulate floating-point arithmetic.
Corresponding intrinsics#
Architectural details#
- Flags
- RFLAGS unchanged. MXCSR floating-point status may be updated.
- Destination
- Writes the low 128 bits; upper vector-register bits are preserved.
- Encoding
66 0F 58 /r- Operands
xmm1read / write · 128 bits (2 × 64) · floatxmm2read · 128 bits (2 × 64) · float
- Coverage
- Selected register-only 128/256-bit legacy and VEX forms. Memory, MMX, EVEX/AVX-512 and scalar floating-point forms are outside this selection.
Exception information & execution requirements
#NM#UD
Feature availability, operating-system vector-state enablement and applicable floating-point exception controls still apply.
Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.
Sources & provenance#
Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.
Intel · ADDPD-Add-Packed-Double-Precision-Floating-Point-Values.xml
- Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7- SHA-256
dafbcbc8e5d8567fd10c16fba10b9552a83fc2efdd3b2149e3d361a69cef900c- Terms
- Intel SDM terms; see License.md
Intel · intrinsics.xml
- Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7- SHA-256
6762a50652a35ef663fd532ed83b789d19bbc2ac7e94b1771f19d666d96c2c30- Terms
- Intel SDM terms; see License.md