All instructionsArm64 · AArch64Memory

STP

Store register pair

Store values through a 64-bit base address, with the selected byte offset and writeback behavior.

Armv8-A

Instruction forms

6 in this sample
FormBitsRequiresEncoding
STP Wt1, Wt2, [Xn|SP{, #offset}]32Armv8-A0010100100xxxxxxxxxxxxxxxxxxxxxx
STP Wt1, Wt2, [Xn|SP, #offset]!32Armv8-A0010100110xxxxxxxxxxxxxxxxxxxxxx
STP Wt1, Wt2, [Xn|SP], #offset32Armv8-A0010100010xxxxxxxxxxxxxxxxxxxxxx
STP Xt1, Xt2, [Xn|SP{, #offset}]64Armv8-A1010100100xxxxxxxxxxxxxxxxxxxxxx
STP Xt1, Xt2, [Xn|SP, #offset]!64Armv8-A1010100110xxxxxxxxxxxxxxxxxxxxxx
STP Xt1, Xt2, [Xn|SP], #offset64Armv8-A1010100010xxxxxxxxxxxxxxxxxxxxxx
32 bits

Operation

Pseudo-C · selected form
old_base = base
address = (old_base + offset) mod 2^64
Store32(address, Rt1)
Store32(address + 4, Rt2)

Simplified pseudocode for the selected form.

What to watch for

  • The base is X0–X30 or SP. The data register may be ZR; loads to ZR still access memory, and stores from ZR supply zero.
  • The operation describes successful ordinary accesses. Data endianness, translation, permissions, alignment and applicable tag checks still apply. No acquire/release ordering is implied.
  • Do not assume the pair is one atomic transfer.

Architectural details

Flags
NZCV unchanged.
Destination
Writes 8 bytes of memory. No base writeback.
Encoding
0010100100xxxxxxxxxxxxxxxxxxxxxx
Operands
  • Wt1read · 32 bits
  • Wt2read · 32 bits
  • Xn|SPread · 64 bits
  • offsetread
  • memory at addresswrite · 64 bits (2 × 32)
Coverage
Selected general-register memory forms with explicitly shown widths and addressing. Register-offset, literal, exclusive, acquire/release and vector forms are outside this selection.
offset
-256 to 252, in steps of 4.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    MRS supplies encoding and availability conditions, not an exhaustive exception model.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Architectural references for this form

    These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.