FDIV

Divide floating-point elements

Divide floating-point elements in the selected vector arrangement.

AdvSIMD + FP32-bit float elements

Similar operations on other architectures:DIVPS_mm_div_psDIVPD_mm_div_pd

Form	Bits	Requires	Encoding
`FDIV Vd.4S,Vn.4S,Vm.4S`	128	AdvSIMD + FP	—
`FDIV Vd.2D,Vn.2D,Vm.2D`	128	AdvSIMD + FP	—

128 bits · 4 × 32-bit elements

Operation#

Pseudo-C · selected form

dst[i] = fp32_operation(a[i] / b[i], FPCR)
update FPSR status or raise a floating-point exception as required

Simplified pseudocode for the selected form.

What to watch for

FPCR supplies rounding and applicable NaN/flush-to-zero controls. NaNs, infinities, signed zeros and subnormals follow the architectural floating-point rules.
This reference does not emulate floating-point execution or its exceptions.

Corresponding intrinsics#

C / C++ · selected form

vdivq_f32

Open example

float32x4_t vdivq_f32( float32x4_t a, float32x4_t b)

#include <arm_neon.h>AdvSIMD + FP

AArch64 mapping documented by ACLE; compiler output depends on optimization and context.

Documented mapping

FDIV Vd.4S,Vn.4S,Vm.4S

Architectural details#

Flags: NZCV unchanged. FPSR floating-point status may change.
Destination: Writes all 128 bits of Vd.
Encoding: Encoding details have not been imported for this form.
Operands: a -> Vn.4S b -> Vm.4S
Vdwrite · 128 bits (4 × 32) · float
Vnread · 128 bits (4 × 32) · float
Vmread · 128 bits (4 × 32) · float
Coverage: Selected FDIV Vd.4S,Vn.4S,Vm.4S arrangement.

Exception information & execution requirements

Complete exception conditions have not been imported.

AdvSIMD/FP access can be trapped by execution-level controls. The ACLE source does not provide an exhaustive exception model.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

Sources & provenance#

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Architectural references for this form

Arm Instruction Set Reference Guide 1.0, D6.62; Parts B1/B2 ↗

These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

Arm · advsimd.md

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View pinned upstream file ↗