All instructionsArm64 · AArch64Compare

TST

Compare by bitwise AND

Compute the flags of ANDS with a zero-register destination; discard the data result.

Armv8-A

Instruction forms

2 in this sample
FormBitsRequiresEncoding
TST Wn, Wm{, shift #amount}32Armv8-A01101010xx0xxxxxxxxxxxxxxxx11111
TST Xn, Xm{, shift #amount}64Armv8-A11101010xx0xxxxxxxxxxxxxxxx11111
32 bits

Operation

Pseudo-C · selected form
result = Rn AND shift_within_width(Rm, shift, amount)
// result discarded
N = result[width-1]; Z = (result == 0)
C = 0; V = 0

Simplified pseudocode for the selected form.

What to watch for

  • Omitted shift means LSL #0. Unlike some A32 operations, shifted-out bits do not set C.
  • Encodes ANDS with Rd = WZR (register number 31). This alias adds no new architectural encoding.

Architectural details

Flags
Sets N and Z from the result. C and V are cleared.
Destination
Updates NZCV only. General-purpose registers and SP are unchanged.
Encoding
01101010xx0xxxxxxxxxxxxxxxx11111
Operands
  • Wnread · 32 bits
  • Wmread · 32 bits
  • shiftread
  • amountread
Coverage
32/64-bit aliases of the selected base encodings. Extended-register and logical-immediate forms are outside this selection.
Alias of
ANDS_32_log_shift with the encoding constraints shown for this form.
shift
LSL, LSR, ASR, ROR.
amount
0 to 31.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    MRS supplies encoding and availability conditions, not an exhaustive exception model.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Architectural references for this form

    These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.