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CMN

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Compute the flags of ADDS with a zero-register destination; discard the data result.

Armv8-A

Instruction forms

4 in this sample
FormBitsRequiresEncoding
CMN Wn, Wm{, shift #amount}32Armv8-A00101011xx0xxxxxxxxxxxxxxxx11111
CMN Wn|WSP, #imm{, LSL #12}32Armv8-A001100010xxxxxxxxxxxxxxxxxx11111
CMN Xn, Xm{, shift #amount}64Armv8-A10101011xx0xxxxxxxxxxxxxxxx11111
CMN Xn|SP, #imm{, LSL #12}64Armv8-A101100010xxxxxxxxxxxxxxxxxx11111
32 bits

Operation

Pseudo-C · selected form
b = shift_within_width(Rm, shift, amount)
result = (Rn + b) mod 2^width
// result discarded
N = most_significant_bit(result)
Z = (result == 0)
C = (unsigned(Rn) + unsigned(b) >= 2^width)
V = signed_overflow(Rn + b, width)

Simplified pseudocode for the selected form.

What to watch for

  • The optional shift is LSL, LSR or ASR, with amount 0–31. Omission means LSL #0. Shifts operate within 32 bits; ASR replicates the sign bit.
  • SP is not an operand of this encoding. WZR/XZR reads as zero and discards writes.
  • Arithmetic wraps at the selected width; it does not saturate.
  • Encodes ADDS with Rd = WZR (register number 31). This alias adds no new architectural encoding.

Architectural details

Flags
N is the result sign bit; Z is set for a zero result; C records unsigned carry out; V records signed overflow. Incoming NZCV is not used.
Destination
Updates NZCV only. General-purpose registers and SP are unchanged.
Encoding
00101011xx0xxxxxxxxxxxxxxxx11111
Operands
  • Wnread · 32 bits
  • Wmread · 32 bits
  • amount (optional)read · unsigned
Coverage
32/64-bit aliases of the selected base encodings. Extended-register and logical-immediate forms are outside this selection.
Alias of
ADDS_32_addsub_shift with the encoding constraints shown for this form.
Shift amount
0 to 31.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    The MRS snapshot supplies encoding and availability conditions, not a complete exception model.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Architectural references for this form

    These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.