SQXTN

Narrow with signed saturation

Narrow with signed saturation in the selected vector arrangement.

AdvSIMD8-bit signed elements

Similar operations on other architectures:PACKSSWB_mm_packs_epi16PACKSSDW_mm_packs_epi32

Form	Bits	Requires	Encoding
`SQXTN Vd.8B,Vn.8H`	64	AdvSIMD	—
`SQXTN Vd.4H,Vn.4S`	64	AdvSIMD	—

64 bits · 8 × 8-bit elements

Operation#

Pseudo-C · selected form

value = a[i]
dst[i] = clamp(value, -128, 127)
if any value was clamped: FPSR.QC = 1

Simplified pseudocode for the selected form.

What to watch for

The “2” form that fills the upper half while preserving the lower half is not selected here.
FPSR.QC is cumulative: saturation sets it, while a nonsaturating operation leaves its previous value unchanged.

Corresponding intrinsics#

C / C++ · selected form

vqmovn_s16

Open example

int8x8_t vqmovn_s16(int16x8_t a)

#include <arm_neon.h>AdvSIMD

AArch64 mapping documented by ACLE; compiler output depends on optimization and context.

Documented mapping

SQXTN Vd.8B,Vn.8H

Architectural details#

Flags: NZCV unchanged. Saturation sets the sticky FPSR.QC bit.
Destination: Writes the low 64 bits of Vd and clears Vd[127:64].
Encoding: Encoding details have not been imported for this form.
Operands: a -> Vn.8H
Vdwrite · 64 bits (8 × 8) · signed
Vnread · 128 bits (8 × 16) · signed
Coverage: Selected SQXTN Vd.8B,Vn.8H arrangement.

Exception information & execution requirements

Complete exception conditions have not been imported.

AdvSIMD/FP access can be trapped by execution-level controls. The ACLE source does not provide an exhaustive exception model.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

Sources & provenance#

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Architectural references for this form

Arm Instruction Set Reference Guide 1.0, D6.200; Parts B1/B2 ↗

These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

Arm · advsimd.md

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View pinned upstream file ↗