All instructionsArm64 · AArch64Shift

LSRV

Variable logical right shift

Use the low count bits to shift or rotate a scalar value.

Armv8-A

Instruction forms

2 in this sample
FormBitsRequiresEncoding
LSRV Wd, Wn, Wm32Armv8-A00011010110xxxxx001001xxxxxxxxxx
LSRV Xd, Xn, Xm64Armv8-A10011010110xxxxx001001xxxxxxxxxx
32 bits

Operation

Pseudo-C · selected form
count = unsigned(Rm) mod width
Rd = logical_right(Rn, count) within width bits

Simplified pseudocode for the selected form.

What to watch for

  • Only the low 5 bits of the count matter; a count equal to the width behaves as zero.
  • ASRV replicates the sign bit; logical shifts fill with zeros; RORV wraps shifted-out bits around.

Architectural details

Flags
NZCV unchanged.
Destination
Writing Wd clears the corresponding X register’s upper 32 bits. Writes to ZR are discarded; SP is not accepted.
Encoding
00011010110xxxxx001001xxxxxxxxxx
Operands
  • Wdwrite · 32 bits
  • Wnread · 32 bits
  • Wmread · 32 bits
Coverage
Selected baseline A64 scalar register forms.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    MRS supplies encoding and availability conditions, not an exhaustive exception model.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Architectural references for this form

    These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.