RET

Return to the caller

Pop the return address and optionally discard additional stack bytes.

x86-64

Instruction forms

2 in this sample
FormBitsRequiresEncoding
RET64x86-64C3
RET imm1664x86-64C2 iw
64 bits

Operation

Pseudo-C · selected form
target = Load64(RSP)
RSP = RSP + 8
RIP = target

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

Source: intel/RET-Return-From-Procedure.xml/0

var new_rsp : Bits(64);
var return_address : Bits(64) := Zero(64);

(return_address[0 +: operand_size], new_rsp) := Pop_Stack?(SS, RSP, operand_size, operand_size);

if CET::Is_Shadow_Stack_Enabled(CPL) then
SSP := CET::Check_Return_RIP?(operand_size, return_address);
endif;

Check_New_RIP?(CS, return_address);

Branch_Near(return_address);

RSP[0 +: stack_address_size] := new_rsp[0 +: stack_address_size] + Zero_Extend(src, stack_address_size);

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

  • Only near control transfers in 64-bit mode are selected. Far transfers, compatibility mode and CET shadow-stack/indirect-branch state are outside the simplified operation.
  • Targets must meet architectural fetch and canonical-address requirements. Stack accesses can fault for CALL/RET.

Architectural details

Flags
RFLAGS unchanged.
Destination
Writes RIP and RSP; reads eight return-address bytes.
Encoding
C3
Operands
    Coverage
    Selected near control transfers in 64-bit execution mode, using a 64-bit stack address size.
    Exception information & execution requirements
    • #UD

    Imported exceptions are checks exposed by this XML form; memory, stack, instruction-fetch and called architectural helpers can introduce additional faults.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Intel · RET-Return-From-Procedure.xml
    Revision
    4ebe7f0ac1bd00f46244c49bb72c503ce368def7
    SHA-256
    11ed321e1a96fe8d9966f0ee548a01bf57b1cb2d07034ea75b271ccc1206d236
    Terms
    Intel SDM terms; see License.md
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.