All instructionsArm64 · AArch64Compare

CSEL

Select on condition

Choose between two registers according to NZCV.

Armv8-A

Instruction forms

2 in this sample
FormBitsRequiresEncoding
CSEL Wd, Wn, Wm, cond32Armv8-A00011010100xxxxxxxxx00xxxxxxxxxx
CSEL Xd, Xn, Xm, cond64Armv8-A10011010100xxxxxxxxx00xxxxxxxxxx
32 bits

Operation

Pseudo-C · selected form
Rd = condition_holds(cond, NZCV) ? Rn : Rm

Simplified pseudocode for the selected form.

What to watch for

  • Both choices have the selected register width. AL and NV select Rn.

Architectural details

Flags
Reads NZCV; leaves NZCV unchanged.
Destination
Writing Wd clears the corresponding X register’s upper 32 bits. Writes to ZR are discarded; SP is not accepted.
Encoding
00011010100xxxxxxxxx00xxxxxxxxxx
Operands
  • Wdwrite · 32 bits
  • Wnread · 32 bits
  • Wmread · 32 bits
  • condread
Coverage
Selected baseline A64 scalar register forms.
cond
EQ, NE, CS, HS, CC, LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV.
Conditions
  • EQ: Z = 1
  • NE: Z = 0
  • CS / HS: C = 1
  • CC / LO: C = 0
  • MI: N = 1
  • PL: N = 0
  • VS: V = 1
  • VC: V = 0
  • HI: C = 1 and Z = 0
  • LS: C = 0 or Z = 1
  • GE: N = V
  • LT: N ≠ V
  • GT: Z = 0 and N = V
  • LE: Z = 1 or N ≠ V
  • AL / NV: Always
Exception information & execution requirements

    Complete exception conditions have not been imported.

    MRS supplies encoding and availability conditions, not an exhaustive exception model.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Architectural references for this form

    These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.