All instructionsArm64 · AArch64Convert

SSHLL

Widen signed elements

Widen signed elements in the selected vector arrangement.

AdvSIMD16-bit signed elements

Similar operations on x86-64:PMOVSXBW_mm_cvtepi8_epi16

Instruction forms

2 in this sample
FormBitsRequiresEncoding
SSHLL Vd.8H,Vn.8B,#0128AdvSIMD—
SSHLL Vd.4S,Vn.4H,#0128AdvSIMD—
128 bits · 8 × 16-bit elements

Operation

Pseudo-C · selected form
dst[i] = sign_extend(a[i], 16)

Simplified pseudocode for the selected form.

What to watch for

  • These selected ACLE mappings fix the shift at zero. Other SSHLL/USHLL shifts and the “2” high-half variants are outside this selection.

Corresponding intrinsics

C / C++ · selected form
vmovl_s8
Open example 
int16x8_t vmovl_s8(int8x8_t a)
#include <arm_neon.h>AdvSIMD

AArch64 mapping documented by ACLE; compiler output depends on optimization and context.

Documented mapping

SSHLL Vd.8H,Vn.8B,#0

Architectural details

Flags
NZCV unchanged.
Destination
Writes all 128 bits of Vd.
Encoding
Encoding details have not been imported for this form.
Operands
a -> Vn.8B
  • Vdwrite · 128 bits (8 × 16) · signed
  • Vnread · 64 bits (8 × 8) · signed
  • shift (fixed in this selection)read · unsigned
Coverage
Selected SSHLL Vd.8H,Vn.8B,#0 arrangement. Shift is fixed at zero.
shift (fixed in this selection)
0.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    AdvSIMD/FP access can be trapped by execution-level controls. The ACLE source does not provide an exhaustive exception model.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Architectural references for this form

    These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

    Arm · advsimd.md
    Revision
    3a8fb2b1145b27ba0a9110ed32f3a6cfdad6c002
    SHA-256
    722dcf758d7a6dbbab54210d55bbce73a6db7691bb4092112375bf096563fd73
    Terms
    CC-BY-SA-4.0 AND Apache-Patent-License
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.