All instructionsArm64 · AArch64Arithmetic

SUBS

Subtract and set flags

Subtract two scalar values and update NZCV; a zero-register destination gives the CMP comparison.

Armv8-A8/16/32-bit · SUB

Similar operations on x86-64:CMP

Instruction forms

4 in this sample
FormBitsRequiresEncoding
SUBS Wd, Wn, Wm{, shift #amount}32Armv8-A01101011xx0xxxxxxxxxxxxxxxxxxxxx
SUBS Wd, Wn|WSP, #imm{, LSL #12}32Armv8-A011100010xxxxxxxxxxxxxxxxxxxxxxx
SUBS Xd, Xn, Xm{, shift #amount}64Armv8-A11101011xx0xxxxxxxxxxxxxxxxxxxxx
SUBS Xd, Xn|SP, #imm{, LSL #12}64Armv8-A111100010xxxxxxxxxxxxxxxxxxxxxxx
64 bits

Operation

Pseudo-C · selected form
b = shift_within_width(Rm, shift, amount)
result = (Rn - b) mod 2^width
Rd = result
N = most_significant_bit(result)
Z = (result == 0)
C = (unsigned(Rn) >= unsigned(b))
V = signed_overflow(Rn - b, width)

Simplified pseudocode for the selected form.

What to watch for

  • The optional shift is LSL, LSR or ASR, with amount 0–63. Omission means LSL #0. Shifts operate within 64 bits; ASR replicates the sign bit.
  • SP is not an operand of this encoding. WZR/XZR reads as zero and discards writes.
  • Arithmetic wraps at the selected width; it does not saturate.
  • CMP is the alias when the destination is XZR. Flags are computed even when the result is discarded.

Architectural details

Flags
N is the result sign bit; Z is set for a zero result; C records no unsigned borrow; V records signed overflow. Incoming NZCV is not used.
Destination
Writes all 64 bits of the destination register. Writes to the zero register are discarded.
Encoding
11101011xx0xxxxxxxxxxxxxxxxxxxxx
Operands
  • Xdwrite · 64 bits
  • Xnread · 64 bits
  • Xmread · 64 bits
  • amount (optional)read · unsigned
Coverage
64-bit A64 shifted-register arithmetic (LSL, LSR, ASR). Extended-register arithmetic is outside this form.
Shift amount
0 to 63.
Exception information & execution requirements

    Complete exception conditions have not been imported.

    The MRS snapshot supplies encoding and availability conditions, not a complete exception model.

    Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

    Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture.

    Sources & provenance

    Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

    Architectural references for this form

    These references support the original explanation. Arm MRS supplies encoding patterns (bit 31 first; x means variable) and architectural conditions, but omits execution pseudocode. ACLE supplies intrinsic mappings. Operand restrictions apply separately.

    Arm · aarchmrs
    Revision
    2026-03_rel
    SHA-256
    bf355d263eed08ef6b3e4e680e6bba3642fa7c3dd0be77ffb4783420041a0860
    Terms
    BSD-3-Clause
    View pinned upstream file ↗

    Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.