AND

Bitwise AND

Combine two scalar inputs and update the logic flags.

x86-64

Form	Bits	Requires	Encoding
`AND r32_dst, r32_src`	32	x86-64	`21 /r`
`AND r32_dst, imm8`	32	x86-64	`83 /4 ib`
`AND r32_dst, imm32`	32	x86-64	`81 /4 iz`
`AND r32_dst, m32_src`	32	x86-64	`23 /r`
`AND m32_dst, r32_src`	32	x86-64	`21 /r`
`AND r64_dst, r64_src`	64	x86-64	`REX.W + 21 /r`
`AND r64_dst, imm8`	64	x86-64	`REX.W + 83 /4 ib`
`AND r64_dst, imm32`	64	x86-64	`REX.W + 81 /4 iz`
`AND r64_dst, m64_src`	64	x86-64	`REX.W + 23 /r`
`AND m64_dst, r64_src`	64	x86-64	`REX.W + 21 /r`

32 bits

Operation#

Pseudo-C · selected form

b = src
result = dst AND b
dst = result
update flags as described

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

Source: intel/AND-Logical-AND.xml/0

let result := src1 and src2;

RFLAGS.OF := 0b0;
RFLAGS.SF := result[operand_size-1];
RFLAGS.ZF := Bit(Is_Zero(result));
RFLAGS.AF := UNSPECIFIED : Bit;
RFLAGS.PF := Bit(Is_Parity_Even(result[0 +: 8]));
RFLAGS.CF := 0b0;

Parameterized by register and element size; from the pinned upstream definition.

Architectural details#

Flags: CF and OF are cleared. SF, ZF and PF reflect the result; AF is undefined.
Destination: Writes the low 32 bits and clears the corresponding 64-bit register’s upper half. Updates arithmetic flags.
Encoding: 21 /r
Operands: r32_dstread / write · 32 bits
r32_srcread · 32 bits
Coverage: Selected 32/64-bit register, immediate and ordinary memory forms in 64-bit execution mode; LOCK and APX forms are outside this selection.

Exception information & execution requirements

#UD

Imported exceptions are checks exposed by this XML form; memory, stack, instruction-fetch and called architectural helpers can introduce additional faults.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance#

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · AND-Logical-AND.xml

Revision: 4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256: ac18e2f2078ddb4592795104a087f9f874ecf7e82f60819b60ecef45a0c14504
Terms: Intel SDM terms; see License.md

View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.

Instruction forms

Operation#

Standard variant

Architectural details#

Sources & provenance#