All instructionsx86-64Compare

CMP

Compare integers

Set arithmetic flags as if subtracting the source from the destination, without storing the difference.

x86-64

Similar operations on Arm64:SUBS

Instruction forms

2 in this sample
FormBitsRequiresEncoding
CMP r32_dst, r32_src32x86-6439 /r
CMP r64_dst, r64_src64x86-64REX.W + 39 /r
64 bits

Operation

Pseudo-C · selected form
temporary = (dst - src) mod 2^width
update OF, SF, ZF, AF, CF, PF
// neither input is overwritten

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

let (result, carry_out, overflow, alternative_carry) := Subtract(src1, src2);

RFLAGS.OF := overflow;
RFLAGS.SF := result[operand_size-1];
RFLAGS.ZF := Bit(Is_Zero(result));
RFLAGS.AF := alternative_carry;
RFLAGS.PF := Bit(Is_Parity_Even(result[0 +: 8]));
RFLAGS.CF := carry_out;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

  • The comparison itself is neither signed nor unsigned; the consuming condition selects the interpretation.

Architectural details

Flags
Updates OF, SF, ZF, AF, CF, and PF.
Destination
Inputs are unchanged.
Encoding
REX.W + 39 /r
Operands
  • r64_dstread
  • r64_srcread
Coverage
Selected 32/64-bit register forms; 64-bit execution mode. LEA uses a 64-bit address size. Other operand and encoding forms are outside this sample.
Exception information & execution requirements
  • #UD

No memory is accessed by this selected form. Consult the source for execution-mode and prefix exceptions.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · CMP-Compare-Two-Operands.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
0e74466f95746fcc25b3823be06d10a61038fefd3bb56f1e6561ce34619bffa5
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.