All instructionsx86-64Convert

MOVZX

Move with zero extension

Copy a narrower value, extending it to the destination width.

x86-64

Instruction forms

8 in this sample
FormBitsRequiresEncoding
MOVZX r32, r832x86-640F B6 /r
MOVZX r32, m832x86-640F B6 /r
MOVZX r32, r1632x86-640F B7 /r
MOVZX r32, m1632x86-640F B7 /r
MOVZX r64, r864x86-64REX.W + 0F B6 /r
MOVZX r64, m864x86-64REX.W + 0F B6 /r
MOVZX r64, r1664x86-64REX.W + 0F B7 /r
MOVZX r64, m1664x86-64REX.W + 0F B7 /r
32 bits

Operation

Pseudo-C · selected form
dst = zero_extend(src, 32)

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

Source: intel/MOVZX-Move-With-Zero-Extend.xml/0

let result := Zero_Extend(src, operand_size);

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

  • A REX prefix prevents use of AH/BH/CH/DH as the byte source.

Architectural details

Flags
RFLAGS unchanged.
Destination
Writes the low 32 bits and clears the corresponding 64-bit register’s upper half.
Encoding
0F B6 /r
Operands
  • r32write · 32 bits · unsigned
  • r8read · 8 bits · unsigned
Coverage
Selected scalar forms in 64-bit execution mode. 8/16-bit arithmetic, APX and unlisted encoding alternatives are outside this selection.
Exception information & execution requirements
  • #UD

Imported exceptions are checks exposed by this XML form; memory, stack, instruction-fetch and called architectural helpers can introduce additional faults.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · MOVZX-Move-With-Zero-Extend.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
26bf248248b7c33094cbd561f914b80abf14626fb1c0366954fbfb6416761530
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.