PACKUSWB

/ VPACKUSWB

Pack signed words into unsigned bytes

Narrow signed 16-bit elements from two inputs into unsigned bytes, clamping values outside 0–255.

SSE28-bit unsigned elements

Form	Bits	Requires	Encoding
`PACKUSWB xmm1, xmm2`	128	SSE2	`66 0F 67 /r`
`VPACKUSWB xmm1, xmm2, xmm3`	128	AVX	`VEX.L0.66.0F.WIG 67 /r`
`VPACKUSWB ymm1, ymm2, ymm3`	256	AVX2	`VEX.L1.66.0F.WIG 67 /r`

128 bits · 16 × 8-bit elements

Operation#

Pseudo-C · selected form

for each 128-bit lane:
  dst[0…7] = clamp(a[0…7], 0, 255)
  dst[8…15] = clamp(b[0…7], 0, 255)

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

let elements := register_size / result_element_size;
var result := Zero(result_size);
let src := (src2 ++ src1);
for i := 0 to elements-1 do
let op := src[i *: element_size];
let r := Unsigned_Saturate(Signed(op), result_element_size);
result[i *: result_element_size] := r;
endfor;

Lane variant

let lanes := register_size / 128;
let elements := 128 / result_element_size;
var result := Zero(result_size);
for lane := 0 to lanes-1 do
let s1 := src1[lane *: 128];
let s2 := src2[lane *: 128];
let src := (s2 ++ s1);
var lane_result := Zero(128);
for i := 0 to elements-1 do
let op := src[i *: element_size];
let r := Unsigned_Saturate(Signed(op), result_element_size);
lane_result[i *: result_element_size] := r;
endfor;
result[lane *: 128] := lane_result;
endfor;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

Input words are signed even though the output bytes are unsigned.
The 256-bit form packs independently inside each 128-bit lane.

Corresponding intrinsics#

C / C++ · selected form

_mm_packus_epi16

__m128i _mm_packus_epi16(__m128i a, __m128i b)

#include <emmintrin.h>SSE2

Documented instruction mapping; a compiler may use an equivalent encoding or optimize the operation away.

Documented mapping

PACKUSWB xmm, xmm

Architectural details#

Flags: Arithmetic flags unchanged.
Destination: Writes the low 128 bits; upper vector-register bits are preserved.
Encoding: 66 0F 67 /r
Operands: xmm1read / write
xmm2read
Coverage: Selected register-only 128/256-bit forms. Memory operands, MMX, and EVEX/AVX-512 forms are outside this sample.

Exception information & execution requirements

#NM
#UD

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance#

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · PACKUSWB-Pack-With-Unsigned-Saturation.xml

Revision: 4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256: 3361c89cd9892a597a5232000b802166440375050b83a2af7921ea2a20bb3298
Terms: Intel SDM terms; see License.md

View pinned upstream file ↗

Intel · intrinsics.xml

Revision: 4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256: 6762a50652a35ef663fd532ed83b789d19bbc2ac7e94b1771f19d666d96c2c30
Terms: Intel SDM terms; see License.md