All instructionsx86-64Logical

POR

/ VPOR

Bitwise OR

Set a bit when it is set in either input.

SSE28-bit bits elements

Similar operations on Arm64:ORRvorrq_u8

Instruction forms

3 in this sample
FormBitsRequiresEncoding
POR xmm1, xmm2128SSE266 0F EB /r
VPOR xmm1, xmm2, xmm3128AVXVEX.L0.66.0F.WIG EB /r
VPOR ymm1, ymm2, ymm3256AVX2VEX.L1.66.0F.WIG EB /r
128 bits · 16 × 8-bit elements

Explore the operation

The interactive explorer is loading. The operation and reference details are available below.

Operation

Pseudo-C · selected form
dst = a OR b

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

let result := src1 or src2;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

  • No element type or signedness is implied by the bitwise operation.

Corresponding intrinsics

C / C++ · selected form
_mm_or_si128
__m128i _mm_or_si128(__m128i a, __m128i b)
#include <emmintrin.h>SSE2

Documented instruction mapping; a compiler may use an equivalent encoding or optimize the operation away.

Documented mapping

POR xmm, xmm

Architectural details

Flags
Arithmetic flags unchanged.
Destination
Writes the low 128 bits; upper vector-register bits are preserved.
Encoding
66 0F EB /r
Operands
  • xmm1read / write
  • xmm2read
Coverage
Selected register-only 128/256-bit forms. Memory operands, MMX, and EVEX/AVX-512 forms are outside this sample.
Exception information & execution requirements
  • #NM
  • #UD

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · POR-Bitwise-Logical-OR.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
aeb73aa4d6a4e41aae89fa60ddf258033baa276bba565828591a2efca103b175
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗
Intel · intrinsics.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
6762a50652a35ef663fd532ed83b789d19bbc2ac7e94b1771f19d666d96c2c30
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.