PSHUFD
/ VPSHUFDShuffle 32-bit elements
Reorder four 32-bit elements in each 128-bit lane using four two-bit selectors in an immediate.
| Form | Bits | Requires | Encoding |
|---|---|---|---|
PSHUFD xmm1, xmm2, imm8 | 128 | SSE2 | 66 0F 70 /r ib |
VPSHUFD xmm1, xmm2, imm8 | 128 | AVX | VEX.L0.66.0F.WIG 70 /r ib |
VPSHUFD ymm1, ymm2, imm8 | 256 | AVX2 | VEX.L1.66.0F.WIG 70 /r ib |
Explore the operation
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Operation#
Pseudo-C · selected form
for each 128-bit lane:
dst[i] = a[(imm8 >> (2*i)) & 3] // i = 0…3Exact upstream semantics
Lane variant
let lanes := register_size / 128;
let elements := 128 / element_size;
let index_size := Log2(elements);
var result := Zero(register_size);
for lane := 0 to lanes-1 do
let s1 := src1[lane *: 128];
var lane_result := Zero(128);
for i := 0 to elements-1 do
let index := Integer::Align_Down(i, elements) + Unsigned(imm8[i % elements *: index_size]);
let r := s1[index *: element_size];
lane_result[i *: element_size] := r;
endfor;
result[lane *: 128] := lane_result;
endfor;What to watch for
- The same immediate is applied independently to each 128-bit lane.
- The intrinsic requires a compile-time immediate.
Corresponding intrinsics#
__m128i _mm_shuffle_epi32(__m128i a, int imm8)Documented mapping
PSHUFD xmm, xmm, imm8
Architectural details#
- Flags
- Arithmetic flags unchanged.
- Destination
- Writes the low 128 bits; upper vector-register bits are preserved.
- Encoding
66 0F 70 /r ib- Operands
xmm1writexmm2read
- Coverage
- Selected register-only 128/256-bit forms. Memory operands, MMX, and EVEX/AVX-512 forms are outside this sample.
- Immediate
- 0 to 255.
Exception information & execution requirements
#NM#UD
Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.
Sources & provenance#
Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.
Intel · PSHUFD-Shuffle-Packed-Doublewords.xml
- Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7- SHA-256
a9ae956fa15ee7ccd9f266fd01c95e3f5158a073a399cedbb3991bb544ab108d- Terms
- Intel SDM terms; see License.md
Intel · intrinsics.xml
- Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7- SHA-256
6762a50652a35ef663fd532ed83b789d19bbc2ac7e94b1771f19d666d96c2c30- Terms
- Intel SDM terms; see License.md