All instructionsx86-64Shift

PSRLW

/ VPSRLW

Shift 16-bit elements right

Shift each 16-bit element right, filling the vacated high bits with zeros.

SSE216-bit unsigned elements

Similar operations on Arm64:USHRvshrq_n_u16

Instruction forms

3 in this sample
FormBitsRequiresEncoding
PSRLW xmm, imm8128SSE266 0F 71 /2 ib
VPSRLW xmm1, xmm2, imm8128AVXVEX.L0.66.0F.WIG 71 /2 ib
VPSRLW ymm1, ymm2, imm8256AVX2VEX.L1.66.0F.WIG 71 /2 ib
128 bits · 8 × 16-bit elements

Explore the operation

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Operation

Pseudo-C · selected form
dst[i] = count >= 16 ? 0 : a[i] >>> count

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

let elements := register_size / element_size;
var result := Zero(register_size);
for i := 0 to elements-1 do
let op1 := src1[i *: element_size];
let count := if shift_size > 64 then Unsigned(shift_distance[0 +: 64]) else Unsigned(shift_distance);
let r := Shift_Right_Logical(op1, count);
result[i *: element_size] := r;
endfor;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

  • This sample covers immediate-count forms.
  • The shift is logical, so it does not extend the sign bit.

Corresponding intrinsics

C / C++ · selected form
_mm_srli_epi16
__m128i _mm_srli_epi16(__m128i a, int imm8)
#include <emmintrin.h>SSE2

Documented instruction mapping; a compiler may use an equivalent encoding or optimize the operation away.

Documented mapping

PSRLW xmm, imm8

Architectural details

Flags
Arithmetic flags unchanged.
Destination
Writes the low 128 bits; upper vector-register bits are preserved.
Encoding
66 0F 71 /2 ib
Operands
  • xmmread / write
  • imm8read
Coverage
Selected register-only 128/256-bit forms. Memory operands, MMX, and EVEX/AVX-512 forms are outside this sample.
Immediate
0 to 255.
Exception information & execution requirements
  • #NM
  • #UD

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · PSRLW-PSRLD-PSRLQ-Shift-Packed-Data-Right-Logical.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
0b7faf1ba3d9b6635cd70cc51716f315aeb678dcebddfe66dd868a6443885c77
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗
Intel · intrinsics.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
6762a50652a35ef663fd532ed83b789d19bbc2ac7e94b1771f19d666d96c2c30
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.