All instructionsx86-64Control flow

JB

/ JC, JNAE

Branch if unsigned below

Test CF = 1; branch when true.

x86-64

Instruction forms

2 in this sample
FormBitsRequiresEncoding
JB rel8—x86-6472 cb
JB rel32—x86-640F 82 cd
No fixed data width

Operation

Pseudo-C · selected form
if CF = 1: RIP = next_RIP + sign_extend(displacement, 64)

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

Source: intel/Jcc-Jump-if-Condition-Is-Met.xml/0

if Condition_Holds(cond) then
let new_rip := Relative_Branch_Wrap(context.operand_size, Next_IP + Sign_Extend(src, 64));
Check_New_RIP?(CS, new_rip);
Branch_Near(new_rip);
endif;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

  • Only near control transfers in 64-bit mode are selected. Far transfers, compatibility mode and CET shadow-stack/indirect-branch state are outside the simplified operation.
  • Targets must meet architectural fetch and canonical-address requirements. Stack accesses can fault for CALL/RET.
  • The displacement is signed and relative to the following instruction.

Architectural details

Flags
Reads CF = 1; leaves RFLAGS unchanged.
Destination
Changes RIP when the condition holds; data registers are unchanged.
Encoding
72 cb
Operands
  • rel8read · 8 bits
Coverage
Selected near rel8/rel32 branches in 64-bit mode.
rel8
-128 to 127.
Conditions
  • unsigned below: CF = 1
Exception information & execution requirements
  • #UD

Imported exceptions are checks exposed by this XML form; memory, stack, instruction-fetch and called architectural helpers can introduce additional faults.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · Jcc-Jump-if-Condition-Is-Met.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
97be450a42a11c8fdb01714fa61096b1ba85f7666c6f33143ab7fa24a331b325
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.