PACKSSWB

/ VPACKSSWB

Pack to signed 8-bit elements with saturation

Clamp signed 16-bit inputs to the signed 8-bit range and pack the results.

SSE28-bit signed elements

Similar operations on Arm64:SQXTNvqmovn_s16

Form	Bits	Requires	Encoding
`PACKSSWB xmm1, xmm2`	128	SSE2	`66 0F 63 /r`
`VPACKSSWB xmm1, xmm2, xmm3`	128	AVX	`VEX.L0.66.0F.WIG 63 /r`
`VPACKSSWB ymm1, ymm2, ymm3`	256	AVX2	`VEX.L1.66.0F.WIG 63 /r`

128 bits · 16 × 8-bit elements

Operation#

Pseudo-C · selected form

for each 128-bit lane:
  dst = concatenate(clamp_each(a, -128, 127),
                    clamp_each(b, -128, 127))

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

Source: intel/PACKSSWB-PACKSSDW-Pack-With-Signed-Saturation.xml/0

let elements := register_size / result_element_size;
var result := Zero(result_size);
let src := (src2 ++ src1);
for i := 0 to elements-1 do
let op := src[i *: element_size];
let r := Signed_Saturate(Signed(op), result_element_size);
result[i *: result_element_size] := r;
endfor;

Lane variant

Source: intel/PACKSSWB-PACKSSDW-Pack-With-Signed-Saturation.xml/1

let lanes := register_size / 128;
let elements := 128 / result_element_size;
var result := Zero(result_size);
for lane := 0 to lanes-1 do
let s1 := src1[lane *: 128];
let s2 := src2[lane *: 128];
let src := (s2 ++ s1);
var lane_result := Zero(128);
for i := 0 to elements-1 do
let op := src[i *: element_size];
let r := Signed_Saturate(Signed(op), result_element_size);
lane_result[i *: result_element_size] := r;
endfor;
result[lane *: 128] := lane_result;
endfor;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

Both inputs are signed. Saturation does not set an integer or SIMD saturation flag.
The AVX2 form packs separately within each 128-bit lane; it does not concatenate two whole 256-bit inputs in order.

Corresponding intrinsics#

C / C++ · selected form

_mm_packs_epi16

Open example

__m128i _mm_packs_epi16(__m128i a, __m128i b)

#include <emmintrin.h>SSE2

Documented instruction mapping; a compiler may use an equivalent encoding or optimize the operation away.

Documented mapping

PACKSSWB xmm, xmm

Architectural details#

Flags: RFLAGS unchanged.
Destination: Writes the low 128 bits; upper vector-register bits are preserved.
Encoding: 66 0F 63 /r
Operands: xmm1read / write · 128 bits (8 × 16) · signed
xmm2read · 128 bits (8 × 16) · signed
Coverage: Selected register-only 128/256-bit legacy and VEX forms. Memory, MMX, EVEX/AVX-512 and scalar floating-point forms are outside this selection.

Exception information & execution requirements

#NM
#UD

Feature availability, operating-system vector-state enablement and applicable floating-point exception controls still apply.

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance#

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · PACKSSWB-PACKSSDW-Pack-With-Signed-Saturation.xml

Revision: 4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256: b5582478a461c4fb5f79cd2d96494d21471aabb29fa24dca95dbe57a4c616149
Terms: Intel SDM terms; see License.md

View pinned upstream file ↗

Intel · intrinsics.xml

Revision: 4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256: 6762a50652a35ef663fd532ed83b789d19bbc2ac7e94b1771f19d666d96c2c30
Terms: Intel SDM terms; see License.md