All instructionsx86-64Rearrange

PSHUFB

/ VPSHUFB

Shuffle bytes

Select a source byte for each output byte using a vector of control bytes. A control byte with its top bit set produces zero.

SSSE38-bit bits elements32-bit · PSHUFD

Similar operations on Arm64:TBLvqtbl1q_u8

Instruction forms

3 in this sample
FormBitsRequiresEncoding
PSHUFB xmm1, xmm2128SSSE366 0F 38 00 /r
VPSHUFB xmm1, xmm2, xmm3128AVXVEX.L0.66.0F38.WIG 00 /r
VPSHUFB ymm1, ymm2, ymm3256AVX2VEX.L1.66.0F38.WIG 00 /r
128 bits · 16 × 8-bit elements

Explore the operation

The interactive explorer is loading. The operation and reference details are available below.

Operation

Pseudo-C · selected form
for each byte i:
  base = floor(i / 16) * 16
  dst[i] = (control[i] & 0x80) ? 0 : a[base + (control[i] & 15)]

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

let elements := register_size / element_size;
let index_size := Log2(elements);
var result := Zero(register_size);
for i := 0 to elements-1 do
let op2 := src2[i *: element_size];
var r : Bits(element_size);
let mask := op2[element_size - 1];
if mask == 0b1 then
r := Zero(element_size);
else
let index := Unsigned(op2[0 +: index_size]);
r := src1[index *: element_size];
endif;
result[i *: element_size] := r;
endfor;

Lane variant

let lanes := register_size / 128;
let elements := 128 / element_size;
let index_size := Log2(elements);
var result := Zero(register_size);
for lane := 0 to lanes-1 do
let s1 := src1[lane *: 128];
let s2 := src2[lane *: 128];
var lane_result := Zero(128);
for i := 0 to elements-1 do
let op2 := s2[i *: element_size];
var r : Bits(element_size);
let mask := op2[element_size - 1];
if mask == 0b1 then
r := Zero(element_size);
else
let index := Unsigned(op2[0 +: index_size]);
r := s1[index *: element_size];
endif;
lane_result[i *: element_size] := r;
endfor;
result[lane *: 128] := lane_result;
endfor;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

  • Each 128-bit lane is independent, including in the 256-bit form.
  • Bits 4–6 of each control byte are ignored. An index of 16 selects byte 0; 128 produces zero.

Corresponding intrinsics

C / C++ · selected form
_mm_shuffle_epi8
__m128i _mm_shuffle_epi8(__m128i a, __m128i b)
#include <tmmintrin.h>SSSE3

Documented instruction mapping; a compiler may use an equivalent encoding or optimize the operation away.

Documented mapping

PSHUFB xmm, xmm

Architectural details

Flags
Arithmetic flags unchanged.
Destination
Writes the low 128 bits; upper vector-register bits are preserved.
Encoding
66 0F 38 00 /r
Operands
  • xmm1read / write
  • xmm2read
Coverage
Selected register-only 128/256-bit forms. Memory operands, MMX, and EVEX/AVX-512 forms are outside this sample.
Exception information & execution requirements
  • #NM
  • #UD

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · PSHUFB-Packed-Shuffle-Bytes.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
c2e74e58745c4c1b8ddf0691eb99b22e6623ef36e38fa8989c1c9eef3dab6e2b
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗
Intel · intrinsics.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
6762a50652a35ef663fd532ed83b789d19bbc2ac7e94b1771f19d666d96c2c30
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.