All instructionsx86-64Arithmetic

PADDUSB

/ VPADDUSB

Add unsigned bytes with saturation

Add corresponding unsigned bytes and clamp each result to 255.

SSE28-bit unsigned elements

Similar operations on Arm64:UQADDvqaddq_u8

Instruction forms

3 in this sample
FormBitsRequiresEncoding
PADDUSB xmm1, xmm2128SSE266 0F DC /r
VPADDUSB xmm1, xmm2, xmm3128AVXVEX.L0.66.0F.WIG DC /r
VPADDUSB ymm1, ymm2, ymm3256AVX2VEX.L1.66.0F.WIG DC /r
128 bits · 16 × 8-bit elements

Explore the operation

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Operation

Pseudo-C · selected form
dst[i] = min(a[i] + b[i], 255)

Simplified pseudocode for the selected form.

Exact upstream semantics

Standard variant

let elements := register_size / element_size;
var result := Zero(register_size);
for i := 0 to elements-1 do
let op1 := src1[i *: element_size];
let op2 := src2[i *: element_size];
let e := Unsigned(op1) + Unsigned(op2);
let r := Unsigned_Saturate(e, element_size);
result[i *: element_size] := r;
endfor;

Parameterized by register and element size; from the pinned upstream definition.

What to watch for

  • Inputs are unsigned bytes.
  • Saturation does not set an x86 arithmetic status flag.

Corresponding intrinsics

C / C++ · selected form
_mm_adds_epu8
__m128i _mm_adds_epu8(__m128i a, __m128i b)
#include <emmintrin.h>SSE2

Documented instruction mapping; a compiler may use an equivalent encoding or optimize the operation away.

Documented mapping

PADDUSB xmm, xmm

Architectural details

Flags
Arithmetic flags unchanged.
Destination
Writes the low 128 bits; upper vector-register bits are preserved.
Encoding
66 0F DC /r
Operands
  • xmm1read / write
  • xmm2read
Coverage
Selected register-only 128/256-bit forms. Memory operands, MMX, and EVEX/AVX-512 forms are outside this sample.
Exception information & execution requirements
  • #NM
  • #UD

Feature availability alone does not guarantee execution: OS state and execution-level controls also apply. Use the linked architecture documentation for the full exception conditions.

Performance measurements are not included in this preview. Latency and throughput depend on the exact form and microarchitecture. Measured data on uops.info ↗

Sources & provenance

Technical fields are imported from pinned upstream files. Explanations and explorer behavior are maintained separately.

Intel · PADDUSB-PADDUSW-Add-Packed-Unsigned-Integers-With-Unsigned-Saturation.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
0aed1b9ca6a8ab6293bac1890395b7bbd7b4e0cd2e883b20e37c2f48c6a72679
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗
Intel · intrinsics.xml
Revision
4ebe7f0ac1bd00f46244c49bb72c503ce368def7
SHA-256
6762a50652a35ef663fd532ed83b789d19bbc2ac7e94b1771f19d666d96c2c30
Terms
Intel SDM terms; see License.md
View pinned upstream file ↗

Intel sources are a documentation preview. Arm ACLE mappings are adapted under CC BY-SA 4.0 with an additional patent license. Arm MRS encoding data is distributed under BSD-3-Clause. © Arm Limited and contributors. Coverage and attribution.